div_clk2.rpt
来自「在采用 320x240 屏的设计实验箱上运行」· RPT 代码 · 共 561 行 · 第 1/2 页
RPT
561 行
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\work\cpld1\vhdl\div_clk2.rpt
div_clk2
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 2/ 96( 2%) 9/ 48( 18%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\work\cpld1\vhdl\div_clk2.rpt
div_clk2
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 10 clk_2M
Device-Specific Information: e:\work\cpld1\vhdl\div_clk2.rpt
div_clk2
** EQUATIONS **
clk_2M : INPUT;
-- Node name is 'clk_5'
-- Equation name is 'clk_5', type is output
clk_5 = _LC3_C11;
-- Node name is ':12' = 'counter0'
-- Equation name is 'counter0', location is LC5_C11, type is buried.
counter0 = DFFE( _EQ001, GLOBAL( clk_2M), VCC, VCC, VCC);
_EQ001 = !counter0 & !counter2
# !counter0 & !counter3
# !counter0 & !_LC1_C11;
-- Node name is ':11' = 'counter1'
-- Equation name is 'counter1', location is LC2_C11, type is buried.
counter1 = DFFE( _EQ002, GLOBAL( clk_2M), VCC, VCC, VCC);
_EQ002 = counter0 & !counter1 & _LC6_C11
# !counter0 & counter1 & _LC6_C11;
-- Node name is ':10' = 'counter2'
-- Equation name is 'counter2', location is LC4_C11, type is buried.
counter2 = DFFE( _EQ003, GLOBAL( clk_2M), VCC, VCC, VCC);
_EQ003 = !counter0 & counter2 & _LC6_C11
# !counter1 & counter2 & _LC6_C11
# counter0 & counter1 & !counter2 & _LC6_C11;
-- Node name is ':9' = 'counter3'
-- Equation name is 'counter3', location is LC1_C1, type is buried.
counter3 = DFFE( _EQ004, GLOBAL( clk_2M), VCC, VCC, VCC);
_EQ004 = counter3 & _LC6_C11 & !_LC7_C11
# !counter3 & _LC6_C11 & _LC7_C11;
-- Node name is ':8' = 'counter4'
-- Equation name is 'counter4', location is LC2_C2, type is buried.
counter4 = DFFE( _EQ005, GLOBAL( clk_2M), VCC, VCC, VCC);
_EQ005 = !counter3 & counter4 & _LC6_C11
# counter4 & _LC6_C11 & !_LC7_C11
# counter3 & !counter4 & _LC6_C11 & _LC7_C11;
-- Node name is ':7' = 'counter5'
-- Equation name is 'counter5', location is LC8_C11, type is buried.
counter5 = DFFE( _EQ006, GLOBAL( clk_2M), VCC, VCC, VCC);
_EQ006 = !counter2 & !counter3 & _LC1_C11
# !counter2 & _LC3_C2
# !counter3 & _LC3_C2
# !_LC1_C11 & _LC3_C2;
-- Node name is ':6' = 'counter6'
-- Equation name is 'counter6', location is LC8_C2, type is buried.
counter6 = DFFE( _EQ007, GLOBAL( clk_2M), VCC, VCC, VCC);
_EQ007 = counter6 & !_LC4_C2 & _LC6_C11
# !counter6 & _LC4_C2 & _LC6_C11;
-- Node name is ':5' = 'counter7'
-- Equation name is 'counter7', location is LC7_C2, type is buried.
counter7 = DFFE( _EQ008, GLOBAL( clk_2M), VCC, VCC, VCC);
_EQ008 = !counter6 & counter7 & _LC6_C11
# counter7 & !_LC4_C2 & _LC6_C11
# counter6 & !counter7 & _LC4_C2 & _LC6_C11;
-- Node name is ':4' = 'counter8'
-- Equation name is 'counter8', location is LC6_C2, type is buried.
counter8 = DFFE( _EQ009, GLOBAL( clk_2M), VCC, VCC, VCC);
_EQ009 = !counter2 & !counter3 & _LC1_C11
# !counter2 & _LC5_C2
# !counter3 & _LC5_C2
# !_LC1_C11 & _LC5_C2;
-- Node name is '|LPM_ADD_SUB:195|addcore:adder|:79' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_C11', type is buried
_LC7_C11 = LCELL( _EQ010);
_EQ010 = counter0 & counter1 & counter2;
-- Node name is '|LPM_ADD_SUB:195|addcore:adder|:91' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_C2', type is buried
_LC4_C2 = LCELL( _EQ011);
_EQ011 = counter3 & counter4 & counter5 & _LC7_C11;
-- Node name is '|LPM_ADD_SUB:195|addcore:adder|:111' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC3_C2', type is buried
_LC3_C2 = LCELL( _EQ012);
_EQ012 = !counter3 & counter5
# counter5 & !_LC7_C11
# !counter4 & counter5
# counter3 & counter4 & !counter5 & _LC7_C11;
-- Node name is '|LPM_ADD_SUB:195|addcore:adder|:114' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC5_C2', type is buried
_LC5_C2 = LCELL( _EQ013);
_EQ013 = !counter7 & counter8
# !counter6 & counter8
# counter8 & !_LC4_C2
# counter6 & counter7 & !counter8 & _LC4_C2;
-- Node name is ':2'
-- Equation name is '_LC3_C11', type is buried
_LC3_C11 = DFFE( _EQ014, GLOBAL( clk_2M), VCC, VCC, VCC);
_EQ014 = !counter2 & !counter3 & _LC1_C11
# !counter3 & _LC3_C11
# !_LC1_C11 & _LC3_C11
# !counter2 & _LC3_C11;
-- Node name is '~90~1'
-- Equation name is '~90~1', location is LC1_C2, type is buried.
-- synthesized logic cell
_LC1_C2 = LCELL( _EQ015);
_EQ015 = counter5 & !counter6 & !counter7 & counter8;
-- Node name is '~90~2'
-- Equation name is '~90~2', location is LC1_C11, type is buried.
-- synthesized logic cell
_LC1_C11 = LCELL( _EQ016);
_EQ016 = !counter0 & !counter1 & !counter4 & _LC1_C2;
-- Node name is '~249~1'
-- Equation name is '~249~1', location is LC6_C11, type is buried.
-- synthesized logic cell
_LC6_C11 = LCELL( _EQ017);
_EQ017 = !_LC1_C11
# counter2 & !counter3
# !counter2 & counter3;
Project Information e:\work\cpld1\vhdl\div_clk2.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:01
Fitter 00:00:05
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:09
Memory Allocated
-----------------
Peak memory allocated during compilation = 12,999K
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