control_cs.v

来自「在采用 320x240 屏的设计实验箱上运行」· Verilog 代码 · 共 48 行

module control_cs( 
        P27,
		hrd,
		hwr,
		h2rd,
		h2wr
); 

input  hwr; 
input  hrd; 
input  P27;
output h2wr; 
output h2rd;

wire pulse; 
reg h2wr;
reg h2rd; 

always @(P27 or hrd or hwr or pulse) //,
begin 
       	if (!P27)begin
			h2wr=hwr; 
			h2rd=hrd;
		end
		else begin
			if(!pulse)begin
				h2wr=1'b0;
				h2rd=1'b1;
				pulse=1'b0;
			end
			else begin
				h2wr=1'b1;
				h2rd=1'b1;
			end
		end

end 

//assign swr_ = hwr_; 
//assign srd_ = hrd_; 
//assign sd_out_oe = !hwr_ & dumy; 
//assign hd_out_oe = !hrd_; 
//assign hd = hd_out_oe ? hd_out : 8'hzz; 
//assign sd = sd_out_oe ? sd_out : 8'hzz; 

endmodule