📄 bidir.rpt
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-- Node name is '|bidir1:26|:48'
-- Equation name is '_LC4_A18', type is buried
_LC4_A18 = LCELL( _EQ003);
_EQ003 = !_LC4_B20 & P05
# _LC4_A18 & _LC4_B20;
-- Node name is '|bidir1:26|:49'
-- Equation name is '_LC1_A18', type is buried
_LC1_A18 = LCELL( _EQ004);
_EQ004 = !_LC4_B20 & P04
# _LC1_A18 & _LC4_B20;
-- Node name is '|bidir1:26|:50'
-- Equation name is '_LC2_B20', type is buried
_LC2_B20 = LCELL( _EQ005);
_EQ005 = !_LC4_B20 & P03
# _LC2_B20 & _LC4_B20;
-- Node name is '|bidir1:26|:51'
-- Equation name is '_LC1_B20', type is buried
_LC1_B20 = LCELL( _EQ006);
_EQ006 = !_LC4_B20 & P02
# _LC1_B20 & _LC4_B20;
-- Node name is '|bidir1:26|:52'
-- Equation name is '_LC1_A21', type is buried
_LC1_A21 = LCELL( _EQ007);
_EQ007 = !_LC4_B20 & P01
# _LC1_A21 & _LC4_B20;
-- Node name is '|bidir1:26|:53'
-- Equation name is '_LC6_A14', type is buried
_LC6_A14 = LCELL( _EQ008);
_EQ008 = !_LC4_B20 & P00
# _LC4_B20 & _LC6_A14;
-- Node name is '|bidir1:26|:87'
-- Equation name is '_LC2_C6', type is buried
_LC2_C6 = LCELL( _EQ009);
_EQ009 = !_LC1_B22 & P0_d7
# _LC1_B22 & _LC2_C6;
-- Node name is '|bidir1:26|:88'
-- Equation name is '_LC4_C11', type is buried
_LC4_C11 = LCELL( _EQ010);
_EQ010 = !_LC1_B22 & P0_d6
# _LC1_B22 & _LC4_C11;
-- Node name is '|bidir1:26|:89'
-- Equation name is '_LC2_C13', type is buried
_LC2_C13 = LCELL( _EQ011);
_EQ011 = !_LC1_B22 & P0_d5
# _LC1_B22 & _LC2_C13;
-- Node name is '|bidir1:26|:90'
-- Equation name is '_LC2_B22', type is buried
_LC2_B22 = LCELL( _EQ012);
_EQ012 = !_LC1_B22 & P0_d4
# _LC1_B22 & _LC2_B22;
-- Node name is '|bidir1:26|:91'
-- Equation name is '_LC6_C24', type is buried
_LC6_C24 = LCELL( _EQ013);
_EQ013 = !_LC1_B22 & P0_d3
# _LC1_B22 & _LC6_C24;
-- Node name is '|bidir1:26|:92'
-- Equation name is '_LC7_C24', type is buried
_LC7_C24 = LCELL( _EQ014);
_EQ014 = !_LC1_B22 & P0_d2
# _LC1_B22 & _LC7_C24;
-- Node name is '|bidir1:26|:93'
-- Equation name is '_LC2_C24', type is buried
_LC2_C24 = LCELL( _EQ015);
_EQ015 = !_LC1_B22 & P0_d1
# _LC1_B22 & _LC2_C24;
-- Node name is '|bidir1:26|:94'
-- Equation name is '_LC1_C24', type is buried
_LC1_C24 = LCELL( _EQ016);
_EQ016 = !_LC1_B22 & P0_d0
# _LC1_B22 & _LC1_C24;
-- Node name is '|DIV_CLK2:29|:12' = '|DIV_CLK2:29|counter0'
-- Equation name is '_LC3_A14', type is buried
_LC3_A14 = DFFE( _EQ017, ale, VCC, VCC, VCC);
_EQ017 = !_LC3_A14 & !_LC8_A16;
-- Node name is '|DIV_CLK2:29|:11' = '|DIV_CLK2:29|counter1'
-- Equation name is '_LC4_A16', type is buried
_LC4_A16 = DFFE( _EQ018, ale, VCC, VCC, VCC);
_EQ018 = _LC3_A14 & !_LC4_A16 & _LC7_A14
# !_LC3_A14 & _LC4_A16 & _LC7_A14;
-- Node name is '|DIV_CLK2:29|:10' = '|DIV_CLK2:29|counter2'
-- Equation name is '_LC5_A16', type is buried
_LC5_A16 = DFFE( _EQ019, ale, VCC, VCC, VCC);
_EQ019 = !_LC3_A14 & _LC5_A16 & _LC7_A14
# !_LC4_A16 & _LC5_A16 & _LC7_A14
# _LC3_A14 & _LC4_A16 & !_LC5_A16 & _LC7_A14;
-- Node name is '|DIV_CLK2:29|:9' = '|DIV_CLK2:29|counter3'
-- Equation name is '_LC7_A16', type is buried
_LC7_A16 = DFFE( _EQ020, ale, VCC, VCC, VCC);
_EQ020 = !_LC1_A16 & !_LC6_A16 & _LC7_A16 & !_LC8_A16
# !_LC1_A16 & _LC6_A16 & !_LC7_A16 & !_LC8_A16;
-- Node name is '|DIV_CLK2:29|:8' = '|DIV_CLK2:29|counter4'
-- Equation name is '_LC1_A15', type is buried
_LC1_A15 = DFFE( _EQ021, ale, VCC, VCC, VCC);
_EQ021 = _LC1_A15 & !_LC1_A16 & !_LC3_A16 & !_LC8_A16
# !_LC1_A15 & !_LC1_A16 & _LC3_A16 & !_LC8_A16;
-- Node name is '|DIV_CLK2:29|:7' = '|DIV_CLK2:29|counter5'
-- Equation name is '_LC5_A15', type is buried
_LC5_A15 = DFFE( _EQ022, ale, VCC, VCC, VCC);
_EQ022 = !_LC1_A15 & _LC5_A15 & _LC7_A14
# !_LC3_A16 & _LC5_A15 & _LC7_A14
# _LC1_A15 & _LC3_A16 & !_LC5_A15 & _LC7_A14;
-- Node name is '|DIV_CLK2:29|:6' = '|DIV_CLK2:29|counter6'
-- Equation name is '_LC8_A15', type is buried
_LC8_A15 = DFFE( _EQ023, ale, VCC, VCC, VCC);
_EQ023 = !_LC2_A15 & _LC7_A14 & _LC8_A15
# _LC2_A15 & _LC7_A14 & !_LC8_A15;
-- Node name is '|DIV_CLK2:29|:5' = '|DIV_CLK2:29|counter7'
-- Equation name is '_LC7_A15', type is buried
_LC7_A15 = DFFE( _EQ024, ale, VCC, VCC, VCC);
_EQ024 = _LC7_A14 & _LC7_A15 & !_LC8_A15
# !_LC2_A15 & _LC7_A14 & _LC7_A15
# _LC2_A15 & _LC7_A14 & !_LC7_A15 & _LC8_A15;
-- Node name is '|DIV_CLK2:29|:4' = '|DIV_CLK2:29|counter8'
-- Equation name is '_LC6_A15', type is buried
_LC6_A15 = DFFE( _EQ025, ale, VCC, VCC, VCC);
_EQ025 = _LC1_A16 & !_LC8_A16
# !_LC3_A15 & _LC6_A15 & !_LC8_A16
# _LC3_A15 & !_LC6_A15 & !_LC8_A16;
-- Node name is '|DIV_CLK2:29|LPM_ADD_SUB:195|addcore:adder|:79' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_A16', type is buried
_LC6_A16 = LCELL( _EQ026);
_EQ026 = _LC3_A14 & _LC4_A16 & _LC5_A16;
-- Node name is '|DIV_CLK2:29|LPM_ADD_SUB:195|addcore:adder|:83' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_A16', type is buried
_LC3_A16 = LCELL( _EQ027);
_EQ027 = _LC3_A14 & _LC4_A16 & _LC5_A16 & _LC7_A16;
-- Node name is '|DIV_CLK2:29|LPM_ADD_SUB:195|addcore:adder|:91' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A15', type is buried
_LC2_A15 = LCELL( _EQ028);
_EQ028 = _LC1_A15 & _LC3_A16 & _LC5_A15;
-- Node name is '|DIV_CLK2:29|LPM_ADD_SUB:195|addcore:adder|:99' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_A15', type is buried
_LC3_A15 = LCELL( _EQ029);
_EQ029 = _LC2_A15 & _LC7_A15 & _LC8_A15;
-- Node name is '|DIV_CLK2:29|:2'
-- Equation name is '_LC5_A14', type is buried
_LC5_A14 = DFFE( _EQ030, ale, VCC, VCC, VCC);
_EQ030 = _LC5_A14 & !_LC8_A16
# _LC1_A16 & !_LC8_A16;
-- Node name is '|DIV_CLK2:29|:71'
-- Equation name is '_LC8_A16', type is buried
!_LC8_A16 = _LC8_A16~NOT;
_LC8_A16~NOT = LCELL( _EQ031);
_EQ031 = !_LC7_A16
# !_LC1_A15
# !_LC5_A15
# !_LC2_A16;
-- Node name is '|DIV_CLK2:29|~90~1'
-- Equation name is '_LC4_A15', type is buried
-- synthesized logic cell
_LC4_A15 = LCELL( _EQ032);
_EQ032 = _LC6_A15 & !_LC7_A15 & !_LC8_A15;
-- Node name is '|DIV_CLK2:29|~90~2'
-- Equation name is '_LC2_A16', type is buried
-- synthesized logic cell
_LC2_A16 = LCELL( _EQ033);
_EQ033 = !_LC3_A14 & _LC4_A15 & !_LC4_A16 & !_LC5_A16;
-- Node name is '|DIV_CLK2:29|:90'
-- Equation name is '_LC1_A16', type is buried
_LC1_A16 = LCELL( _EQ034);
_EQ034 = !_LC1_A15 & _LC2_A16 & !_LC5_A15 & !_LC7_A16;
-- Node name is '|DIV_CLK2:29|~249~1'
-- Equation name is '_LC7_A14', type is buried
-- synthesized logic cell
_LC7_A14 = LCELL( _EQ035);
_EQ035 = !_LC1_A16 & !_LC8_A16;
-- Node name is '|74373b:28|:12'
-- Equation name is '_LC2_A14', type is buried
_LC2_A14 = LCELL( _EQ036);
_EQ036 = ale & P00
# !ale & _LC2_A14;
-- Node name is '|74373b:28|:13'
-- Equation name is '_LC2_A12', type is buried
_LC2_A12 = LCELL( _EQ037);
_EQ037 = ale & P01
# !ale & _LC2_A12;
-- Node name is '|74373b:28|:14'
-- Equation name is '_LC1_B10', type is buried
_LC1_B10 = LCELL( _EQ038);
_EQ038 = ale & P02
# !ale & _LC1_B10;
-- Node name is '|74373b:28|:15'
-- Equation name is '_LC4_B10', type is buried
_LC4_B10 = LCELL( _EQ039);
_EQ039 = ale & P03
# !ale & _LC4_B10;
-- Node name is '|74373b:28|:16'
-- Equation name is '_LC1_A7', type is buried
_LC1_A7 = LCELL( _EQ040);
_EQ040 = ale & P04
# !ale & _LC1_A7;
-- Node name is '|74373b:28|:17'
-- Equation name is '_LC1_A6', type is buried
_LC1_A6 = LCELL( _EQ041);
_EQ041 = ale & P05
# !ale & _LC1_A6;
-- Node name is '|74373b:28|:18'
-- Equation name is '_LC7_C15', type is buried
_LC7_C15 = LCELL( _EQ042);
_EQ042 = ale & P06
# !ale & _LC7_C15;
-- Node name is '|74373b:28|:19'
-- Equation name is '_LC5_C15', type is buried
_LC5_C15 = LCELL( _EQ043);
_EQ043 = ale & P07
# !ale & _LC5_C15;
-- Node name is ':68'
-- Equation name is '_LC4_B20', type is buried
!_LC4_B20 = _LC4_B20~NOT;
_LC4_B20~NOT = LCELL( _EQ044);
_EQ044 = !hwr & !P2_7;
-- Node name is ':69'
-- Equation name is '_LC1_B22', type is buried
!_LC1_B22 = _LC1_B22~NOT;
_LC1_B22~NOT = LCELL( _EQ045);
_EQ045 = !hrd & !P2_7;
Project Informationg:\research\tjx-experiment\esd-5_sample\dso_fft\vhdl\bidir.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 15,562K
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