📄 bidir.rpt
字号:
49 - - - 16 TRI 0 1 0 1 P0_d6
48 - - - 15 TRI 0 1 0 1 P0_d7
73 - - A -- TRI 0 1 0 2 P00
78 - - - 24 TRI 0 1 0 2 P01
79 - - - 24 TRI 0 1 0 2 P02
80 - - - 23 TRI 0 1 0 2 P03
81 - - - 22 TRI 0 1 0 2 P04
83 - - - 13 TRI 0 1 0 2 P05
3 - - - 12 TRI 0 1 0 2 P06
5 - - - 05 TRI 0 1 0 2 P07
23 - - B -- OUTPUT 0 1 0 0 srd
24 - - B -- OUTPUT 0 1 0 0 swr
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:g:\research\tjx-experiment\esd-5_sample\dso_fft\vhdl\bidir.rpt
bidir
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - A 09 LCELL s 1 0 1 0 addh0~1
- 1 - C 01 LCELL s 1 0 1 0 addh1~1
- 1 - B 08 LCELL s 1 0 1 0 addh2~1
- 2 - B 03 LCELL s 1 0 1 0 addh3~1
- 2 - B 04 LCELL s 1 0 1 0 addh4~1
- 1 - C 15 OR2 0 2 1 0 |bidir1:26|:46
- 3 - C 15 OR2 0 2 1 0 |bidir1:26|:47
- 4 - A 18 OR2 0 2 1 0 |bidir1:26|:48
- 1 - A 18 OR2 0 2 1 0 |bidir1:26|:49
- 2 - B 20 OR2 0 2 1 0 |bidir1:26|:50
- 1 - B 20 OR2 0 2 1 0 |bidir1:26|:51
- 1 - A 21 OR2 0 2 1 0 |bidir1:26|:52
- 6 - A 14 OR2 0 2 1 0 |bidir1:26|:53
- 2 - C 06 OR2 0 2 1 0 |bidir1:26|:87
- 4 - C 11 OR2 0 2 1 0 |bidir1:26|:88
- 2 - C 13 OR2 0 2 1 0 |bidir1:26|:89
- 2 - B 22 OR2 0 2 1 0 |bidir1:26|:90
- 6 - C 24 OR2 0 2 1 0 |bidir1:26|:91
- 7 - C 24 OR2 0 2 1 0 |bidir1:26|:92
- 2 - C 24 OR2 0 2 1 0 |bidir1:26|:93
- 1 - C 24 OR2 0 2 1 0 |bidir1:26|:94
- 8 - B 01 LCELL s 1 0 1 0 cs~1
- 6 - A 16 AND2 0 3 0 1 |DIV_CLK2:29|LPM_ADD_SUB:195|addcore:adder|:79
- 3 - A 16 AND2 0 4 0 3 |DIV_CLK2:29|LPM_ADD_SUB:195|addcore:adder|:83
- 2 - A 15 AND2 0 3 0 3 |DIV_CLK2:29|LPM_ADD_SUB:195|addcore:adder|:91
- 3 - A 15 AND2 0 3 0 1 |DIV_CLK2:29|LPM_ADD_SUB:195|addcore:adder|:99
- 5 - A 14 DFFE 1 2 1 0 |DIV_CLK2:29|:2
- 6 - A 15 DFFE 1 3 0 1 |DIV_CLK2:29|counter8 (|DIV_CLK2:29|:4)
- 7 - A 15 DFFE 1 3 0 2 |DIV_CLK2:29|counter7 (|DIV_CLK2:29|:5)
- 8 - A 15 DFFE 1 2 0 3 |DIV_CLK2:29|counter6 (|DIV_CLK2:29|:6)
- 5 - A 15 DFFE 1 3 0 3 |DIV_CLK2:29|counter5 (|DIV_CLK2:29|:7)
- 1 - A 15 DFFE 1 3 0 4 |DIV_CLK2:29|counter4 (|DIV_CLK2:29|:8)
- 7 - A 16 DFFE 1 3 0 3 |DIV_CLK2:29|counter3 (|DIV_CLK2:29|:9)
- 5 - A 16 DFFE 1 3 0 3 |DIV_CLK2:29|counter2 (|DIV_CLK2:29|:10)
- 4 - A 16 DFFE 1 2 0 4 |DIV_CLK2:29|counter1 (|DIV_CLK2:29|:11)
- 3 - A 14 DFFE 1 1 0 5 |DIV_CLK2:29|counter0 (|DIV_CLK2:29|:12)
- 8 - A 16 OR2 ! 0 4 0 6 |DIV_CLK2:29|:71
- 4 - A 15 AND2 s 0 3 0 1 |DIV_CLK2:29|~90~1
- 2 - A 16 AND2 s 0 4 0 2 |DIV_CLK2:29|~90~2
- 1 - A 16 AND2 0 4 0 5 |DIV_CLK2:29|:90
- 7 - A 14 AND2 s 0 2 0 5 |DIV_CLK2:29|~249~1
- 4 - C 24 SOFT s r 0 1 1 0 srd~fit~in1
- 6 - B 20 SOFT s r 0 1 1 0 swr~fit~in1
- 4 - B 20 AND2 ! 2 0 0 9 :68
- 1 - B 22 AND2 ! 2 0 0 9 :69
- 2 - A 14 LCELL 1 1 1 0 |74373b:28|:12
- 2 - A 12 LCELL 1 1 1 0 |74373b:28|:13
- 1 - B 10 LCELL 1 1 1 0 |74373b:28|:14
- 4 - B 10 LCELL 1 1 1 0 |74373b:28|:15
- 1 - A 07 LCELL 1 1 1 0 |74373b:28|:16
- 1 - A 06 LCELL 1 1 1 0 |74373b:28|:17
- 7 - C 15 LCELL 1 1 1 0 |74373b:28|:18
- 5 - C 15 LCELL 1 1 1 0 |74373b:28|:19
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:g:\research\tjx-experiment\esd-5_sample\dso_fft\vhdl\bidir.rpt
bidir
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 8/ 96( 8%) 0/ 48( 0%) 11/ 48( 22%) 2/16( 12%) 1/16( 6%) 1/16( 6%)
B: 7/ 96( 7%) 6/ 48( 12%) 1/ 48( 2%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
C: 8/ 96( 8%) 3/ 48( 6%) 7/ 48( 14%) 0/16( 0%) 4/16( 25%) 1/16( 6%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 2/24( 8%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 2/24( 8%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
13: 3/24( 12%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
14: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 2/24( 8%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
16: 2/24( 8%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
17: 2/24( 8%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
18: 2/24( 8%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
19: 3/24( 12%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
20: 2/24( 8%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
21: 2/24( 8%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
22: 3/24( 12%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
23: 2/24( 8%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
24: 6/24( 25%) 0/4( 0%) 0/4( 0%) 2/4( 50%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:g:\research\tjx-experiment\esd-5_sample\dso_fft\vhdl\bidir.rpt
bidir
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 18 ale
Device-Specific Information:g:\research\tjx-experiment\esd-5_sample\dso_fft\vhdl\bidir.rpt
bidir
** EQUATIONS **
ale : INPUT;
hrd : INPUT;
hwr : INPUT;
P2_6 : INPUT;
P2_7 : INPUT;
P20 : INPUT;
P21 : INPUT;
P22 : INPUT;
P23 : INPUT;
P24 : INPUT;
-- Node name is 'addh0~1'
-- Equation name is 'addh0~1', location is LC3_A9, type is buried.
-- synthesized logic cell
_LC3_A9 = LCELL( P20);
-- Node name is 'addh0'
-- Equation name is 'addh0', type is output
addh0 = _LC3_A9;
-- Node name is 'addh1~1'
-- Equation name is 'addh1~1', location is LC1_C1, type is buried.
-- synthesized logic cell
_LC1_C1 = LCELL( P21);
-- Node name is 'addh1'
-- Equation name is 'addh1', type is output
addh1 = _LC1_C1;
-- Node name is 'addh2~1'
-- Equation name is 'addh2~1', location is LC1_B8, type is buried.
-- synthesized logic cell
_LC1_B8 = LCELL( P22);
-- Node name is 'addh2'
-- Equation name is 'addh2', type is output
addh2 = _LC1_B8;
-- Node name is 'addh3~1'
-- Equation name is 'addh3~1', location is LC2_B3, type is buried.
-- synthesized logic cell
_LC2_B3 = LCELL( P23);
-- Node name is 'addh3'
-- Equation name is 'addh3', type is output
addh3 = _LC2_B3;
-- Node name is 'addh4~1'
-- Equation name is 'addh4~1', location is LC2_B4, type is buried.
-- synthesized logic cell
_LC2_B4 = LCELL( P24);
-- Node name is 'addh4'
-- Equation name is 'addh4', type is output
addh4 = _LC2_B4;
-- Node name is 'address0'
-- Equation name is 'address0', type is output
address0 = _LC2_A14;
-- Node name is 'address1'
-- Equation name is 'address1', type is output
address1 = _LC2_A12;
-- Node name is 'address2'
-- Equation name is 'address2', type is output
address2 = _LC1_B10;
-- Node name is 'address3'
-- Equation name is 'address3', type is output
address3 = _LC4_B10;
-- Node name is 'address4'
-- Equation name is 'address4', type is output
address4 = _LC1_A7;
-- Node name is 'address5'
-- Equation name is 'address5', type is output
address5 = _LC1_A6;
-- Node name is 'address6'
-- Equation name is 'address6', type is output
address6 = _LC7_C15;
-- Node name is 'address7'
-- Equation name is 'address7', type is output
address7 = _LC5_C15;
-- Node name is 'clk_32k'
-- Equation name is 'clk_32k', type is output
clk_32k = _LC5_A14;
-- Node name is 'cs'
-- Equation name is 'cs', type is output
cs = _LC8_B1;
-- Node name is 'cs~1'
-- Equation name is 'cs~1', location is LC8_B1, type is buried.
-- synthesized logic cell
_LC8_B1 = LCELL( P2_6);
-- Node name is 'P0_d0'
-- Equation name is 'P0_d0', type is bidir
P0_d0 = TRI(_LC6_A14, !_LC4_B20);
-- Node name is 'P0_d1'
-- Equation name is 'P0_d1', type is bidir
P0_d1 = TRI(_LC1_A21, !_LC4_B20);
-- Node name is 'P0_d2'
-- Equation name is 'P0_d2', type is bidir
P0_d2 = TRI(_LC1_B20, !_LC4_B20);
-- Node name is 'P0_d3'
-- Equation name is 'P0_d3', type is bidir
P0_d3 = TRI(_LC2_B20, !_LC4_B20);
-- Node name is 'P0_d4'
-- Equation name is 'P0_d4', type is bidir
P0_d4 = TRI(_LC1_A18, !_LC4_B20);
-- Node name is 'P0_d5'
-- Equation name is 'P0_d5', type is bidir
P0_d5 = TRI(_LC4_A18, !_LC4_B20);
-- Node name is 'P0_d6'
-- Equation name is 'P0_d6', type is bidir
P0_d6 = TRI(_LC3_C15, !_LC4_B20);
-- Node name is 'P0_d7'
-- Equation name is 'P0_d7', type is bidir
P0_d7 = TRI(_LC1_C15, !_LC4_B20);
-- Node name is 'P00'
-- Equation name is 'P00', type is bidir
P00 = TRI(_LC1_C24, !_LC1_B22);
-- Node name is 'P01'
-- Equation name is 'P01', type is bidir
P01 = TRI(_LC2_C24, !_LC1_B22);
-- Node name is 'P02'
-- Equation name is 'P02', type is bidir
P02 = TRI(_LC7_C24, !_LC1_B22);
-- Node name is 'P03'
-- Equation name is 'P03', type is bidir
P03 = TRI(_LC6_C24, !_LC1_B22);
-- Node name is 'P04'
-- Equation name is 'P04', type is bidir
P04 = TRI(_LC2_B22, !_LC1_B22);
-- Node name is 'P05'
-- Equation name is 'P05', type is bidir
P05 = TRI(_LC2_C13, !_LC1_B22);
-- Node name is 'P06'
-- Equation name is 'P06', type is bidir
P06 = TRI(_LC4_C11, !_LC1_B22);
-- Node name is 'P07'
-- Equation name is 'P07', type is bidir
P07 = TRI(_LC2_C6, !_LC1_B22);
-- Node name is 'srd'
-- Equation name is 'srd', type is output
srd = !_LC4_C24;
-- Node name is 'srd~fit~in1'
-- Equation name is 'srd~fit~in1', location is LC4_C24, type is buried.
-- synthesized logic cell
_LC4_C24 = LCELL(!_LC1_B22);
-- Node name is 'swr'
-- Equation name is 'swr', type is output
swr = !_LC6_B20;
-- Node name is 'swr~fit~in1'
-- Equation name is 'swr~fit~in1', location is LC6_B20, type is buried.
-- synthesized logic cell
_LC6_B20 = LCELL(!_LC4_B20);
-- Node name is '|bidir1:26|:46'
-- Equation name is '_LC1_C15', type is buried
_LC1_C15 = LCELL( _EQ001);
_EQ001 = !_LC4_B20 & P07
# _LC1_C15 & _LC4_B20;
-- Node name is '|bidir1:26|:47'
-- Equation name is '_LC3_C15', type is buried
_LC3_C15 = LCELL( _EQ002);
_EQ002 = !_LC4_B20 & P06
# _LC3_C15 & _LC4_B20;
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