📄 bidir.rpt
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Project Informationg:\research\tjx-experiment\esd-5_sample\dso_fft\vhdl\bidir.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 02/25/2007 18:01:59
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
bidir EPF10K10LC84-3 10 17 16 0 0 % 53 9 %
User Pins: 10 17 16
Project Informationg:\research\tjx-experiment\esd-5_sample\dso_fft\vhdl\bidir.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
bidir@28 addh0
bidir@27 addh1
bidir@21 addh2
bidir@22 addh3
bidir@6 addh4
bidir@47 address0
bidir@39 address1
bidir@38 address2
bidir@37 address3
bidir@36 address4
bidir@35 address5
bidir@30 address6
bidir@29 address7
bidir@19 ale
bidir@18 clk_32k
bidir@25 cs
bidir@42 hrd
bidir@44 hwr
bidir@58 P0_d0
bidir@54 P0_d1
bidir@53 P0_d2
bidir@52 P0_d3
bidir@51 P0_d4
bidir@50 P0_d5
bidir@49 P0_d6
bidir@48 P0_d7
bidir@73 P00
bidir@78 P01
bidir@2 P2_6
bidir@84 P2_7
bidir@79 P02
bidir@80 P03
bidir@81 P04
bidir@83 P05
bidir@3 P06
bidir@5 P07
bidir@16 P20
bidir@11 P21
bidir@10 P22
bidir@9 P23
bidir@8 P24
bidir@23 srd
bidir@24 swr
Project Informationg:\research\tjx-experiment\esd-5_sample\dso_fft\vhdl\bidir.rpt
** FILE HIERARCHY **
|bidir1:26|
|74373b:28|
|div_clk2:29|
|div_clk2:29|lpm_add_sub:148|
|div_clk2:29|lpm_add_sub:148|addcore:adder|
|div_clk2:29|lpm_add_sub:148|altshift:result_ext_latency_ffs|
|div_clk2:29|lpm_add_sub:148|altshift:carry_ext_latency_ffs|
|div_clk2:29|lpm_add_sub:148|altshift:oflow_ext_latency_ffs|
|div_clk2:29|lpm_add_sub:195|
|div_clk2:29|lpm_add_sub:195|addcore:adder|
|div_clk2:29|lpm_add_sub:195|altshift:result_ext_latency_ffs|
|div_clk2:29|lpm_add_sub:195|altshift:carry_ext_latency_ffs|
|div_clk2:29|lpm_add_sub:195|altshift:oflow_ext_latency_ffs|
Device-Specific Information:g:\research\tjx-experiment\esd-5_sample\dso_fft\vhdl\bidir.rpt
bidir
***** Logic for device 'bidir' compiled without errors.
Device: EPF10K10LC84-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
^
C
R O
E N
S V G G F
E a C N N _ ^
R d C P D P D # D n
P P P P V d P I P 2 I 2 P I P P P P T O C
2 2 2 2 E h 0 N 0 _ N _ 0 N 0 0 0 0 C N E
1 2 3 4 D 4 7 T 6 6 T 7 5 T 4 3 2 1 K E O
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
^DATA0 | 12 74 | #TDO
^DCLK | 13 73 | P00
^nCE | 14 72 | RESERVED
#TDI | 15 71 | RESERVED
P20 | 16 70 | RESERVED
RESERVED | 17 69 | RESERVED
clk_32k | 18 68 | GNDINT
ale | 19 67 | RESERVED
VCCINT | 20 66 | RESERVED
addh2 | 21 65 | RESERVED
addh3 | 22 EPF10K10LC84-3 64 | RESERVED
srd | 23 63 | VCCINT
swr | 24 62 | RESERVED
cs | 25 61 | RESERVED
GNDINT | 26 60 | RESERVED
addh1 | 27 59 | RESERVED
addh0 | 28 58 | P0_d0
address7 | 29 57 | #TMS
address6 | 30 56 | #TRST
^MSEL0 | 31 55 | ^nSTATUS
^MSEL1 | 32 54 | P0_d1
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
V ^ a a a a a V G h G h V G a P P P P P P
C n d d d d d C N r N w C N d 0 0 0 0 0 0
C C d d d d d C D d D r C D d _ _ _ _ _ _
I O r r r r r I I I I I r d d d d d d
N N e e e e e N N N N N e 7 6 5 4 3 2
T F s s s s s T T T T T s
I s s s s s s
G 5 4 3 2 1 0
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information:g:\research\tjx-experiment\esd-5_sample\dso_fft\vhdl\bidir.rpt
bidir
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A6 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 2/22( 9%)
A7 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 2/22( 9%)
A9 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
A12 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 2/22( 9%)
A14 5/ 8( 62%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 5/22( 22%)
A15 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 5/22( 22%)
A16 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 6/22( 27%)
A18 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
A21 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 2/22( 9%)
B1 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
B3 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
B4 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 1/22( 4%)
B8 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
B10 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
B20 4/ 8( 50%) 3/ 8( 37%) 2/ 8( 25%) 0/2 0/2 4/22( 18%)
B22 2/ 8( 25%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
C1 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
C6 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 2/22( 9%)
C11 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 2/22( 9%)
C13 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 2/22( 9%)
C15 4/ 8( 50%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 4/22( 18%)
C24 5/ 8( 62%) 5/ 8( 62%) 0/ 8( 0%) 0/2 0/2 5/22( 22%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 4/6 ( 66%)
Total I/O pins used: 39/53 ( 73%)
Total logic cells used: 53/576 ( 9%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 2.81/4 ( 70%)
Total fan-in: 149/2304 ( 6%)
Total input pins required: 10
Total input I/O cell registers required: 0
Total output pins required: 17
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 16
Total reserved pins required 0
Total logic cells required: 53
Total flipflops required: 10
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Logic cells inserted for fitting: 2
Synthesized logic cells: 11/ 576 ( 1%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 1 1 0 1 0 0 1 0 0 5 8 8 0 2 0 0 1 0 0 0 28/0
B: 1 0 1 1 0 0 0 1 0 2 0 0 0 0 0 0 0 0 0 0 4 0 2 0 0 12/0
C: 1 0 0 0 0 1 0 0 0 0 1 0 0 1 0 4 0 0 0 0 0 0 0 0 5 13/0
Total: 2 0 1 1 0 2 1 1 1 2 1 1 0 1 5 12 8 0 2 0 4 1 2 0 5 53/0
Device-Specific Information:g:\research\tjx-experiment\esd-5_sample\dso_fft\vhdl\bidir.rpt
bidir
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
19 - - A -- INPUT 0 0 0 18 ale
42 - - - -- INPUT 0 0 0 1 hrd
44 - - - -- INPUT 0 0 0 1 hwr
58 - - C -- BIDIR 0 1 0 1 P0_d0
54 - - - 21 BIDIR 0 1 0 1 P0_d1
53 - - - 20 BIDIR 0 1 0 1 P0_d2
52 - - - 19 BIDIR 0 1 0 1 P0_d3
51 - - - 18 BIDIR 0 1 0 1 P0_d4
50 - - - 17 BIDIR 0 1 0 1 P0_d5
49 - - - 16 BIDIR 0 1 0 1 P0_d6
48 - - - 15 BIDIR 0 1 0 1 P0_d7
73 - - A -- BIDIR 0 1 0 2 P00
78 - - - 24 BIDIR 0 1 0 2 P01
2 - - - -- INPUT 0 0 0 1 P2_6
84 - - - -- INPUT 0 0 0 2 P2_7
79 - - - 24 BIDIR 0 1 0 2 P02
80 - - - 23 BIDIR 0 1 0 2 P03
81 - - - 22 BIDIR 0 1 0 2 P04
83 - - - 13 BIDIR 0 1 0 2 P05
3 - - - 12 BIDIR 0 1 0 2 P06
5 - - - 05 BIDIR 0 1 0 2 P07
16 - - A -- INPUT 0 0 0 1 P20
11 - - - 01 INPUT 0 0 0 1 P21
10 - - - 01 INPUT 0 0 0 1 P22
9 - - - 02 INPUT 0 0 0 1 P23
8 - - - 03 INPUT 0 0 0 1 P24
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:g:\research\tjx-experiment\esd-5_sample\dso_fft\vhdl\bidir.rpt
bidir
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
28 - - C -- OUTPUT 0 1 0 0 addh0
27 - - C -- OUTPUT 0 1 0 0 addh1
21 - - B -- OUTPUT 0 1 0 0 addh2
22 - - B -- OUTPUT 0 1 0 0 addh3
6 - - - 04 OUTPUT 0 1 0 0 addh4
47 - - - 14 OUTPUT 0 1 0 0 address0
39 - - - 11 OUTPUT 0 1 0 0 address1
38 - - - 10 OUTPUT 0 1 0 0 address2
37 - - - 09 OUTPUT 0 1 0 0 address3
36 - - - 07 OUTPUT 0 1 0 0 address4
35 - - - 06 OUTPUT 0 1 0 0 address5
30 - - C -- OUTPUT 0 1 0 0 address6
29 - - C -- OUTPUT 0 1 0 0 address7
18 - - A -- OUTPUT 0 1 0 0 clk_32k
25 - - B -- OUTPUT 0 1 0 0 cs
58 - - C -- TRI 0 1 0 1 P0_d0
54 - - - 21 TRI 0 1 0 1 P0_d1
53 - - - 20 TRI 0 1 0 1 P0_d2
52 - - - 19 TRI 0 1 0 1 P0_d3
51 - - - 18 TRI 0 1 0 1 P0_d4
50 - - - 17 TRI 0 1 0 1 P0_d5
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