div_clk2.vhd

来自「在采用 320x240 屏的设计实验箱上运行」· VHDL 代码 · 共 30 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
entity div_clk2 is
	port(
		clk_2M		: in std_logic; 
        clk_5	 	: out std_logic 
    );  
end div_clk2;

architecture v1 of div_clk2 is
signal counter : std_logic_vector(8 downto 0) ;
begin
	process(clk_2M)
        begin
		if clk_2M'event and clk_2M='1' then--"100101100"采128点时
			if counter="100111000" then   --  10011100
				clk_5<='0';
				counter<="000000000" ;
			elsif counter="100000000" then
				clk_5<='1';
				counter<=counter+1;
			else 
				counter<=counter+1 ;
			end if ;
		end if ;
     end process;    
end v1;