📄 bidir1.rpt
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Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 3/24( 12%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
08: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 3/24( 12%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\work\cpld1\vhdl\bidir1.rpt
bidir1
** EQUATIONS **
dumy : INPUT;
hrd_ : INPUT;
hwr_ : INPUT;
-- Node name is 'hd0'
-- Equation name is 'hd0', type is bidir
hd0 = TRI(_LC4_C14, GLOBAL(!hrd_));
-- Node name is 'hd1'
-- Equation name is 'hd1', type is bidir
hd1 = TRI(_LC2_B8, GLOBAL(!hrd_));
-- Node name is 'hd2'
-- Equation name is 'hd2', type is bidir
hd2 = TRI(_LC1_B9, GLOBAL(!hrd_));
-- Node name is 'hd3'
-- Equation name is 'hd3', type is bidir
hd3 = TRI(_LC8_C14, GLOBAL(!hrd_));
-- Node name is 'hd4'
-- Equation name is 'hd4', type is bidir
hd4 = TRI(_LC1_C14, GLOBAL(!hrd_));
-- Node name is 'hd5'
-- Equation name is 'hd5', type is bidir
hd5 = TRI(_LC1_B8, GLOBAL(!hrd_));
-- Node name is 'hd6'
-- Equation name is 'hd6', type is bidir
hd6 = TRI(_LC8_B9, GLOBAL(!hrd_));
-- Node name is 'hd7'
-- Equation name is 'hd7', type is bidir
hd7 = TRI(_LC2_B9, GLOBAL(!hrd_));
-- Node name is 'sd0'
-- Equation name is 'sd0', type is bidir
sd0 = TRI(_LC8_C8, _LC1_B17);
-- Node name is 'sd1'
-- Equation name is 'sd1', type is bidir
sd1 = TRI(_LC2_B17, _LC1_B17);
-- Node name is 'sd2'
-- Equation name is 'sd2', type is bidir
sd2 = TRI(_LC5_C8, _LC1_B17);
-- Node name is 'sd3'
-- Equation name is 'sd3', type is bidir
sd3 = TRI(_LC6_C8, _LC1_B17);
-- Node name is 'sd4'
-- Equation name is 'sd4', type is bidir
sd4 = TRI(_LC3_B17, _LC1_B17);
-- Node name is 'sd5'
-- Equation name is 'sd5', type is bidir
sd5 = TRI(_LC1_C8, _LC1_B17);
-- Node name is 'sd6'
-- Equation name is 'sd6', type is bidir
sd6 = TRI(_LC7_B17, _LC1_B17);
-- Node name is 'sd7'
-- Equation name is 'sd7', type is bidir
sd7 = TRI(_LC4_B17, _LC1_B17);
-- Node name is 'srd_'
-- Equation name is 'srd_', type is output
srd_ = _LC6_C14;
-- Node name is 'srd_~1'
-- Equation name is 'srd_~1', location is LC6_C14, type is buried.
-- synthesized logic cell
_LC6_C14 = LCELL( hrd_);
-- Node name is 'swr_'
-- Equation name is 'swr_', type is output
swr_ = _LC5_B17;
-- Node name is 'swr_~1'
-- Equation name is 'swr_~1', location is LC5_B17, type is buried.
-- synthesized logic cell
_LC5_B17 = LCELL( hwr_);
-- Node name is ':26'
-- Equation name is '_LC1_B17', type is buried
_LC1_B17 = LCELL( _EQ001);
_EQ001 = dumy & !hwr_;
-- Node name is ':46'
-- Equation name is '_LC4_B17', type is buried
_LC4_B17 = LCELL( _EQ002);
_EQ002 = hd7 & !hwr_
# hwr_ & _LC4_B17;
-- Node name is ':47'
-- Equation name is '_LC7_B17', type is buried
_LC7_B17 = LCELL( _EQ003);
_EQ003 = hd6 & !hwr_
# hwr_ & _LC7_B17;
-- Node name is ':48'
-- Equation name is '_LC1_C8', type is buried
_LC1_C8 = LCELL( _EQ004);
_EQ004 = hd5 & !hwr_
# hwr_ & _LC1_C8;
-- Node name is ':49'
-- Equation name is '_LC3_B17', type is buried
_LC3_B17 = LCELL( _EQ005);
_EQ005 = hd4 & !hwr_
# hwr_ & _LC3_B17;
-- Node name is ':50'
-- Equation name is '_LC6_C8', type is buried
_LC6_C8 = LCELL( _EQ006);
_EQ006 = hd3 & !hwr_
# hwr_ & _LC6_C8;
-- Node name is ':51'
-- Equation name is '_LC5_C8', type is buried
_LC5_C8 = LCELL( _EQ007);
_EQ007 = hd2 & !hwr_
# hwr_ & _LC5_C8;
-- Node name is ':52'
-- Equation name is '_LC2_B17', type is buried
_LC2_B17 = LCELL( _EQ008);
_EQ008 = hd1 & !hwr_
# hwr_ & _LC2_B17;
-- Node name is ':53'
-- Equation name is '_LC8_C8', type is buried
_LC8_C8 = LCELL( _EQ009);
_EQ009 = hd0 & !hwr_
# hwr_ & _LC8_C8;
-- Node name is ':87'
-- Equation name is '_LC2_B9', type is buried
_LC2_B9 = LCELL( _EQ010);
_EQ010 = !hrd_ & sd7
# hrd_ & _LC2_B9;
-- Node name is ':88'
-- Equation name is '_LC8_B9', type is buried
_LC8_B9 = LCELL( _EQ011);
_EQ011 = !hrd_ & sd6
# hrd_ & _LC8_B9;
-- Node name is ':89'
-- Equation name is '_LC1_B8', type is buried
_LC1_B8 = LCELL( _EQ012);
_EQ012 = !hrd_ & sd5
# hrd_ & _LC1_B8;
-- Node name is ':90'
-- Equation name is '_LC1_C14', type is buried
_LC1_C14 = LCELL( _EQ013);
_EQ013 = !hrd_ & sd4
# hrd_ & _LC1_C14;
-- Node name is ':91'
-- Equation name is '_LC8_C14', type is buried
_LC8_C14 = LCELL( _EQ014);
_EQ014 = !hrd_ & sd3
# hrd_ & _LC8_C14;
-- Node name is ':92'
-- Equation name is '_LC1_B9', type is buried
_LC1_B9 = LCELL( _EQ015);
_EQ015 = !hrd_ & sd2
# hrd_ & _LC1_B9;
-- Node name is ':93'
-- Equation name is '_LC2_B8', type is buried
_LC2_B8 = LCELL( _EQ016);
_EQ016 = !hrd_ & sd1
# hrd_ & _LC2_B8;
-- Node name is ':94'
-- Equation name is '_LC4_C14', type is buried
_LC4_C14 = LCELL( _EQ017);
_EQ017 = !hrd_ & sd0
# hrd_ & _LC4_C14;
Project Information e:\work\cpld1\vhdl\bidir1.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:01
Fitter 00:00:05
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:07
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,128K
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