bvdisrs.c

intel xscale pxa270的完整wince4.2 BSP包

//
// MMC ISR
//
//  Inputs:
//      ra  -   return address of the interrupted routine
//
int MMCISR(unsigned int ra)
{
    volatile XLLP_INTC_T *v_pICReg;
    v_pICReg = (volatile XLLP_INTC_T *)INTC_BASE_U_VIRTUAL;

	INTC_MMC_INT_DIS(v_pICReg->icmr);

#if (WINCEOSVER > 400)
    if (fIntrTime) 
	{
        dwIsrTime1 = PerfCountSinceTick();
        wNumInterrupts++;
    }
#endif

	return SYSINTR_SDMMC;
}

//
// KEYPADISR
//
// KeyPad ISR
//
//  Inputs:
//      ra  -   return address of the interrupted routine
//
int KEYPADISR(unsigned int ra)
{
    volatile XLLP_INTC_T *v_pICReg;
    v_pICReg = (volatile XLLP_INTC_T *)INTC_BASE_U_VIRTUAL;


	INTC_KEYPAD_INT_DIS(v_pICReg->icmr);

#if (WINCEOSVER > 400)
    if (fIntrTime) 
	{
        dwIsrTime1 = PerfCountSinceTick();
        wNumInterrupts++;
    }
#endif

	return SYSINTR_KEYPAD;
}

//
// UDCISR
//
// UDC Device Controller ISR (USB Function)
//
//  Inputs:
//      ra  -   return address of the interrupted routine
//
int UDCISR(unsigned int ra)
{
    volatile XLLP_INTC_T *v_pICReg;

    v_pICReg = (volatile XLLP_INTC_T *)INTC_BASE_U_VIRTUAL;

    //
    // UDC - USB Device Controller
	// mask the USB interrupt
    //
	INTC_USBC_INT_DIS(v_pICReg->icmr);

#if (WINCEOSVER > 400)
    if (fIntrTime) 
	{
        dwIsrTime1 = PerfCountSinceTick();
        wNumInterrupts++;
    }
#endif

	return SYSINTR_USB_CLIENT;
}

//
// FFUARTISR
//
// FullFeatured UART
//
//  Inputs:
//      ra  -   return address of the interrupted routine
//
int FFUARTISR(unsigned int ra)
{
    volatile XLLP_INTC_T *v_pICReg;

    v_pICReg = (volatile XLLP_INTC_T *)INTC_BASE_U_VIRTUAL;

	//
    // FFUART interrupt 
    // mask the interrupt
    //
	INTC_FFUART_INT_DIS(v_pICReg->icmr);

#if (WINCEOSVER > 400)
    if (fIntrTime) 
	{
        dwIsrTime1 = PerfCountSinceTick();
        wNumInterrupts++;
    }
#endif

	return SYSINTR_SERIAL;
}

//
// BTUARTISR
//
// BlueTooth UART
//
//  Inputs:
//      ra  -   return address of the interrupted routine
//
int BTUARTISR(unsigned int ra)
{
    volatile XLLP_INTC_T *v_pICReg;

    v_pICReg = (volatile XLLP_INTC_T *)INTC_BASE_U_VIRTUAL;

	//
    // BTUART interrupt 
    // mask the interrupt
    //
	INTC_BTUART_INT_DIS(v_pICReg->icmr);

#if (WINCEOSVER > 400)
    if (fIntrTime) 
	{
        dwIsrTime1 = PerfCountSinceTick();
        wNumInterrupts++;
    }
#endif

	return SYSINTR_SERIAL2;
}

//
// STDUARTISR
//
// Standard UART - IrDA 
//
//  Inputs:
//      ra  -   return address of the interrupted routine
//
int STDUARTISR(unsigned int ra)
{
    volatile XLLP_INTC_T *v_pICReg;

    v_pICReg = (volatile XLLP_INTC_T *)INTC_BASE_U_VIRTUAL;

    //
    // STDUART interrupt - IrDA port
    // mask the interrupt
    //
	INTC_STUART_INT_DIS(v_pICReg->icmr);

#if (WINCEOSVER > 400)
    if (fIntrTime) 
	{
        dwIsrTime1 = PerfCountSinceTick();
        wNumInterrupts++;
    }
#endif

	return SYSINTR_IR;
}

//
// DMACISR
//
// DMA Controller ISR
//
//  Inputs:
//      ra  -   return address of the interrupted routine
//

int DMACISR(unsigned int ra)
{
    volatile XLLP_INTC_T *v_pICReg;
	volatile DMAC_REGS	*v_pDMAReg;

    v_pDMAReg = (volatile DMAC_REGS *)DMAC_BASE_U_VIRTUAL; 
    v_pICReg = (volatile XLLP_INTC_T *)INTC_BASE_U_VIRTUAL;
		
	// 
	// DMAC interrupt (Interrupt Mask 25)
	// 
    //
    // Mask interrupt
    //
	INTC_DMAC_INT_DIS(v_pICReg->icmr);

#if (WINCEOSVER > 400)
    if (fIntrTime) 
	{
        dwIsrTime1 = PerfCountSinceTick();
        wNumInterrupts++;
    }
#endif

	// Determine the nature of the interrupt

	//
	//AC97 Audio Interrupt
	//
//	if (v_pDMAReg->dint & DMA_AUDIO_INTR)	// The DMAC had some kind of AUDIO interrupt
//	{
//		return SYSINTR_AUDIO;
//	}
	//===hzh
	if (v_pDMAReg->dint & DMA_AUDIO_INTR)
	{
		//RETAILMSG(1,(TEXT("AI\r\n")));	//hzh
		return SYSINTR_AUDIO;
	}
	//===
	// The DMA "engine" will handle the remaining DMA interrupts.			
	return SYSINTR_DMA;
}

//
// Chainable ISR
//
//  Inputs:
//      ra  -   return address of the interrupted routine
//
//  Call the kernel and chain to the installable ISR
// 
int ChainableISR(unsigned int ra)
{
	DWORD			sysIntrValue,
					devID;
    unsigned long	devBit;
    volatile XLLP_INTC_T  *v_pICReg;

    v_pICReg = (volatile XLLP_INTC_T *)INTC_BASE_U_VIRTUAL;

	//
	// Get interrupting device ID and bit mask
	// 
	devID = v_pICReg->ichp & 0x0000001F;

    //
    // Chain to the ISR, if one is installed
    //
	sysIntrValue = NKCallIntChain ((BYTE)devID);	// Device Interrupt ID
	
	if (sysIntrValue == SYSINTR_CHAIN)
	{
        //
        // No installable isr to handle this interrupt
		// disable the interrupt
        //
		devBit = (0x1 << devID);
		v_pICReg->icmr &= ~devBit;
		sysIntrValue = SYSINTR_NOP;
    }

	return sysIntrValue;

}


//
// PMU ISR
//
// Needs to be modified for FIQ
//
//  Inputs:
//      ra  -   return address of the interrupted routine
//
int PMUISR(unsigned int ra)
{
    volatile XLLP_INTC_T *v_pICReg;

    v_pICReg = (volatile XLLP_INTC_T *)INTC_BASE_U_VIRTUAL;

    //
    // Service the PMU interrupt
    //

    //
    // PVTuneInterrupt is initialized when the callback routine 
    // is registered, otherwise it's NULL.
    //
    if(PVTuneInterrupt)
    {
        SampleInput     StateData;
		BOOL			bBufferFull;


		//
		// Mask interrupt
		//
        INTC_PMU_INT_DIS (v_pICReg->icmr);


        // Grab sample data for VTune
        // ra (interrupted address),
        // SPSR,
        // TID,
        // PID
	    // 
        StateData.r14 = ra;
        StateData.spsr = XSC1GetSPSR();
        StateData.tid = GetCurrentThreadId();
        StateData.pid = GetCurrentProcessId();

        //
        // Call the PMU interrupt callback routine to buffer the
        // processor state.  Callback returns TRUE if post-processing
        // is necessary (buffer is full). If post-processing is needed,
        // signal VTune PMU IST (SYSINTR_PMU), otherwise return SYSINTR_NOP.
        //
        // Note:  PVTuneInterrupt initialized in oemioctl in 
        //        PMU_ENABLE_IRQ processing.  Resolved to address kernel
        //        can access in PMU API.
        //
		//
		bBufferFull = PVTuneInterrupt(&StateData);

		//
		// Unmask interrupt
		//
        INTC_PMU_INT_EN (v_pICReg->icmr);


		if (bBufferFull)
		{
            return SYSINTR_PMU;
		}
    }
    else
    {
        //
        // No PMU interrupt registered -> disable the interrupt
        //
        INTC_PMU_INT_DIS (v_pICReg->icmr);
        bPMURunning = FALSE;
    }
    //
    // No post-processing needed.
    //
    return SYSINTR_NOP;
}


//
// USBOHCISTATISR
//
// USB Host OHCI Controller Status ISR (USB Host)
//
//  Inputs:
//      ra  -   return address of the interrupted routine
//
int USBOHCIISR(unsigned int ra)
{
    volatile XLLP_INTC_T *v_pICReg;

    volatile BLR_REGS    *v_pBLReg;
    v_pBLReg    = (volatile BLR_REGS *)FPGA_REGS_BASE_U_VIRTUAL;
    
	v_pICReg = (volatile XLLP_INTC_T *)INTC_BASE_U_VIRTUAL;

    //
	// mask the USB Host interrupt
    //
	INTC_USBOHCI_INT_DIS(v_pICReg->icmr);

#if (WINCEOSVER > 400)
    if (fIntrTime) 
	{
        dwIsrTime1 = PerfCountSinceTick();
        wNumInterrupts++;
    }
#endif

	return SYSINTR_OHCI_MDD;
}

//
// USBOHCIEVENTISR
//
// USB Host OHCI Controller Event: abort, power, misc. ISR (USB Host)
//
//  Inputs:
//      ra  -   return address of the interrupted routine
//
int USBNONOHCIISR(unsigned int ra)
{
    volatile XLLP_INTC_T *v_pICReg;

    volatile BLR_REGS    *v_pBLReg;
    v_pBLReg    = (volatile BLR_REGS *)FPGA_REGS_BASE_U_VIRTUAL;

    v_pICReg = (volatile XLLP_INTC_T *)INTC_BASE_U_VIRTUAL;

    //
	// mask the USB Host interrupt
    //
	INTC_USBNONOHCI_INT_DIS(v_pICReg->icmr);

#if (WINCEOSVER > 400)
    if (fIntrTime) 
	{
        dwIsrTime1 = PerfCountSinceTick();
        wNumInterrupts++;
    }
#endif

	return SYSINTR_OHCI_PDD;
}

//
// Bulverde Capture interface ISR
//
// Delivers an End Of Frame interrupt
//
//  Inputs:
//      ra  -   return address of the interrupted routine
//

int BvdCIISR(unsigned int ra)
{
	volatile XLLP_INTC_T *v_pICReg;

	v_pICReg = (volatile XLLP_INTC_T *)INTC_BASE_U_VIRTUAL;

	INTC_CAPTURE_INT_DIS(v_pICReg->icmr2);

	return SYSINTR_CAMERA_INTERFACE;
}