plx9054.h

intel xscale pxa270的完整wince4.2 BSP包

/*****************************************************************************
*Filename: PLX9054.H - Defines & structures for PCI adapter
*                     
* SanDisk Host Developer's Toolkit
*
* Copyright (c) 1997-1998 SanDisk Corporation
* All rights reserved.
*
* Description: 
*       Defines & structures for PCI adapter
*
****************************************************************************/
/* PLX 9054 PCI controller definitions */


#ifndef __PLX9054__

#include "sdtypes.h"


#define lengthof(x) ((sizeof(x))/(sizeof(x[0])))



/************************************************************************/
/*      Manifest Constants                                              */
/************************************************************************/

#define CAPLIST_BIT     0x0010  /* capabilities list? */

#define MAX_LINE        512     /* max length of a line in .PCI files */
#define MAX_VENDOR_NAME 50      /* max length of vendor's name */
#define MAX_DEVICE_NAME 50      /* max length of device name */
#define MAX_VENDOR_DATA 16384   /* maximum data per vendor */

 
/*====================================================================
              Constants
====================================================================*/

/*--------------------------------------------------------------------
      SANDISK PCI IDs
--------------------------------------------------------------------*/


//These were the values used on the beta board
//#define SD_DEVICE_ID            0x5130
//#define SD_VENDOR_ID            0x107F

#define SD_DEVICE_ID            0x1100
#define SD_VENDOR_ID            0x15b7

/*--------------------------------------------------------------------
      PCI interface configuration register constants.
      These values can be manipulated to affect performance.
--------------------------------------------------------------------*/
#define SD_CACHE_LINE_SIZE      0x08
#define SD_LATENCY_TIME         0xE0
#define SD_FIFO_THRESHOLD       0x02    /* makes fifo 32 entries deep */
#define SD_STD_CLOCK_RATE       40      /* for 20 MHZ */



/*--------------------------------------------------------------------
 |  definitions for "command" field of PCI Configuration Registers
  --------------------------------------------------------------------*/
#define PCI_CRC_IO                    0x0001
#define PCI_CRC_MEM                   0x0002
#define PCI_CRC_PCI_MASTER            0x0004
#define PCI_CRC_SPECIAL_CYCLE         0x0008
#define PCI_CRC_MEM_WRITE_INV         0x0010
#define PCI_CRC_VGA                   0x0020
#define PCI_CRC_PARITY                0x0040
#define PCI_CRC_WAIT_CYLCLE           0x0080
#define PCI_CRC_SERR                  0x0100
#define PCI_CRC_BACK_TO_BACK          0x0200
#define PCI_CRC_INIT_COMMAND          0xF9000157


/*--------------------------------------------------------------------
 |  definitions for "status" field of PCI Configuration Registers
  --------------------------------------------------------------------*/
#define PCI_CRS_BACK_TO_BACK          0x0080
#define PCI_CRS_DATA_PARITY           0x0100
#define PCI_CRS_TIMING9               0x0200
#define PCI_CRS_TIMING10              0x0400
#define PCI_CRS_SIG_T_ABORT           0x0800
#define PCI_CRS_RCV_T_ABORT           0x1000
#define PCI_CRS_RCV_M_ABORT           0x2000
#define PCI_CRS_SYSTEM_ERR            0x4000
#define PCI_CRS_PARITY_ERR            0x8000


#define PCI_CRIO_IO_SPACE             0x00000001
#define PCI_CRIO_MEM_SPACE            0x00000001
#define PCI_CRIO_EXP_ROM              0x00000001

/*--------------------------------------------------------------------
 |  definitions for offsets each field into the PCI Configuration register.
  --------------------------------------------------------------------*/
#define PCI_CR_VENDOR_ID              0x0000
#define PCI_CR_DEVICE_ID              0x0002
#define PCI_CR_COMMAND                0x0004
#define PCI_CR_STATUS                 0x0006
#define PCI_CR_REVISION_ID            0x0008
#define PCI_CR_CLASS_PI               0x0009
#define PCI_CR_CLASS_SUB              0x000A
#define PCI_CR_CLASS                  0x000B
#define PCI_CR_CACHE_LINE             0x000C
#define PCI_CR_LATENCY_TIMER          0x000D
#define PCI_CR_HEADER_TYPE            0x000E
#define PCI_CR_BIST                   0x000F
#define PCI_CR_IO_BASE_ADDR           0x0010
#define PCI_CR_MEM_BASE_ADDR          0x0014
#define PCI_CR_EXP_ROM_ADDR           0x0030
#define PCI_CR_INTR_LINE              0x003C
#define PCI_CR_INTR_PIN               0x003D
#define PCI_CR_MIN_GRANT              0x003E
#define PCI_CR_MAX_LATENCY            0x003F


/* DOS interface */
#define PCI_FUNCTION_ID               0xB1


#define PCI_BIOS_PRESENT              0x01
#define PCI_FIND_DEVICE_ID            0x02
#define PCI_FIND_DEVICE_CLASS         0x03
#define PCI_READ_CONFIG_BYTE          0x08
#define PCI_READ_CONFIG_WORD          0x09
#define PCI_READ_CONFIG_DWORD         0x0A
#define PCI_WRITE_CONFIG_BYTE         0x0B
#define PCI_WRITE_CONFIG_WORD         0x0C
#define PCI_WRITE_CONFIG_DWORD        0x0D


/* " ICP" return value signature from PCI system */
#define PCI_SIGNATURE                 0x20494350



/*====================================================================
 |      Typedefs
  ====================================================================*/

/*--------------------------------------------------------------------
 |  Structure for PCI Configuration Registers and
 |      NOTE: Data is aligned for configuration address UINT16.
  --------------------------------------------------------------------*/




/*--------------------------------------------------------------------
      Some general constants
--------------------------------------------------------------------*/
#define SD_DEFAULT_TIMEOUT      10


typedef struct pci_adapter
{
        UINT32  portIO;
        INT16   intr;
} ADAPTER, *PADAPTER;


#define __PLX9054__

#endif  /* __PLX9054__ */