2410init.s

嵌入式开发原代码达盛2410开发板运行程序2410的板子

;/*
;************************************************************************************************************
;*				        				北京精仪达盛科技有限公司
;*                                     	     研    发    部
;*
;*                                 	     http://www.techshine.com
;*
;*--------------------------------------------- 文件信息 ----------------------------------------------------                                      
;*
;* 文件名称 : 2410INIT.S
;* 文件功能 : 该文件为ARM9硬件平台的C语言启动代码，用于分配中断向量表，初始化ISR地址，初始化堆栈空间，
;*            初始化应用程序执行环境，配置存储器系统，设定时钟周期，呼叫主应用程序。
;* 补充说明 : 基于S3C2410的ARM9硬件平台的启动代码
;*-------------------------------------------- 最新版本信息 -------------------------------------------------
;* 修改作者 : ARM开发小组
;* 修改日期 : 2005/08/23
;* 版本声明 : V1.0.1
;*-------------------------------------------- 历史版本信息 -------------------------------------------------
;* 文件作者 : ARM开发小组
;* 创建日期 : 2004/04/20
;* 版本声明 : v1.0.0
;*-----------------------------------------------------------------------------------------------------------
;*-----------------------------------------------------------------------------------------------------------
;************************************************************************************************************
;*/
	GET option.s
	GET memcfg.s
	GET 2410addr.s

BIT_SELFREFRESH EQU	(1<<22)

;//Pre-defined constants
USERMODE    EQU 	0x10
FIQMODE     EQU 	0x11
IRQMODE     EQU 	0x12
SVCMODE     EQU 	0x13
ABORTMODE   EQU 	0x17
UNDEFMODE   EQU 	0x1b
MODEMASK    EQU 	0x1f
NOINT       EQU 	0xc0

;//The location of stacks
UserStack	EQU	(_STACK_BASEADDRESS-0x3800)			;//0x33ff4800 ~ 
SVCStack    EQU	(_STACK_BASEADDRESS-0x2800) 	    ;//0x33ff5800 ~
UndefStack	EQU	(_STACK_BASEADDRESS-0x2400) 		;//0x33ff5c00 ~
AbortStack	EQU	(_STACK_BASEADDRESS-0x2000) 		;//0x33ff6000 ~
IRQStack    EQU	(_STACK_BASEADDRESS-0x1000)		    ;//0x33ff7000 ~
FIQStack	EQU	(_STACK_BASEADDRESS-0x0)			;//0x33ff8000 ~ 

;//Check if tasm.exe(armasm -16 ...@ADS 1.0) is used.
	GBLL    THUMBCODE
	[ {CONFIG} = 16 
		THUMBCODE SETL  {TRUE}
	    CODE32
    	|   
THUMBCODE SETL  {FALSE}
    	]

    MACRO
	MOV_PC_LR
    	[ THUMBCODE
            bx lr
    	|
            mov	pc,lr
    	]
	MEND

    MACRO
	MOVEQ_PC_LR
    	[ THUMBCODE
    	    bxeq lr
    	|
            moveq pc,lr
    	]
	MEND

    	MACRO
$HandlerLabel HANDLER $HandleLabel

$HandlerLabel
	sub	sp,sp,#4        	;//decrement sp(to store jump address)
	stmfd	sp!,{r0}        ;//PUSH the work register to stack(lr does't push because it return to original address)
	ldr     r0,=$HandleLabel;//load the address of HandleXXX to r0
	ldr     r0,[r0]         ;//load the contents(service routine start address) of HandleXXX
	str     r0,[sp,#4]      ;//store the contents(ISR) of HandleXXX to stack
	ldmfd   sp!,{r0,pc}     ;//POP the work register and pc(jump to ISR)
	MEND
	

	IMPORT  |Image$$RO$$Limit|  ;// End of ROM code (=start of ROM data)
	IMPORT  |Image$$RW$$Base|   ;// Base of RAM to initialise
	IMPORT  |Image$$ZI$$Base|   ;// Base and limit of area
	IMPORT  |Image$$ZI$$Limit|  ;// to zero initialise
	
	;//IMPORT  Main    ;// The main entry of mon program 
	
	AREA    Init,CODE,READONLY

	ENTRY 

	; //1)The code, which converts to Big-endian, should be in little endian code.
	; //2)The following little endian code will be compiled in Big-Endian mode. 
	; //  The code byte order should be changed as the memory bus width.
	; //3)The pseudo instruction,DCD can't be used here because the linker generates error.
	ASSERT	:DEF:ENDIAN_CHANGE
	[ ENDIAN_CHANGE
	    ASSERT  :DEF:ENTRY_BUS_WIDTH
	    [ ENTRY_BUS_WIDTH=32
		b	ChangeBigEndian	    ;//DCD 0xea000007 
	    ]
	    
	    [ ENTRY_BUS_WIDTH=16
		andeq	r14,r7,r0,lsl #20   ;//DCD 0x0007ea00
	    ]
	    
	    [ ENTRY_BUS_WIDTH=8
		streq	r0,[r0,-r10,ror #1] ;//DCD 0x070000ea
            ]
	|
	    b	ResetHandler  
    	]
	b	HandlerUndef	;//handler for Undefined mode
	b	HandlerSWI		;//handler for SWI interrupt
	b	HandlerPabort	;//handler for PAbort
	b	HandlerDabort	;//handler for DAbort
	b	.				;//reserved
	b	HandlerIRQ		;//handler for IRQ interrupt 
	b	HandlerFIQ		;//handler for FIQ interrupt

;//@0x20
	b	EnterPWDN
ChangeBigEndian
;//@0x24
	[ ENTRY_BUS_WIDTH=32
	    DCD	0xee110f10	;//0xee110f10 => mrc p15,0,r0,c1,c0,0
	    DCD	0xe3800080	;//0xe3800080 => orr r0,r0,#0x80;  //Big-endian
	    DCD	0xee010f10	;//0xee010f10 => mcr p15,0,r0,c1,c0,0
	]
	[ ENTRY_BUS_WIDTH=16
	    DCD 0x0f10ee11
	    DCD 0x0080e380	
	    DCD 0x0f10ee01	
	]
	[ ENTRY_BUS_WIDTH=8
	    DCD 0x100f11ee	
	    DCD 0x800080e3	
	    DCD 0x100f01ee	
    	]
	DCD 0xffffffff  ;//swinv 0xffffff is similar with NOP and run well in both endian mode. 
	DCD 0xffffffff
	DCD 0xffffffff
	DCD 0xffffffff
	DCD 0xffffffff
	b ResetHandler
	
;//Function for entering power down mode
;// 1. SDRAM should be in self-refresh mode.
;// 2. All interrupt should be maksked for SDRAM/DRAM self-refresh.
;// 3. LCD controller should be disabled for SDRAM/DRAM self-refresh.
;// 4. The I-cache may have to be turned on. 
;// 5. The location of the following code may have not to be changed.

;//void EnterPWDN(int CLKCON); 
EnterPWDN			
	mov r2,r0					;//r2=rCLKCON
	tst r0,#0x8					;//POWER_OFF mode?
	bne ENTER_POWER_OFF

ENTER_STOP	
	ldr r0,=REFRESH		
	ldr r3,[r0]					;//r3=rREFRESH	
	mov r1, r3
	orr r1, r1, #BIT_SELFREFRESH
	str r1, [r0]				;//Enable SDRAM self-refresh

	mov r1,#16	   				;//wait until self-refresh is issued. may not be needed.
0	subs r1,r1,#1
	bne %B0

	ldr r0,=CLKCON				;//enter STOP mode.
	str r2,[r0]    

	mov r1,#32
0	subs r1,r1,#1				;//1) wait until the STOP mode is in effect.
	bne %B0						;//2) Or wait here until the CPU&Peripherals will be turned-off
								;//   Entering POWER_OFF mode, only the reset by wake-up is available.

	ldr r0,=REFRESH 			;//exit from SDRAM self refresh mode.
	str r3,[r0]
	
	MOV_PC_LR

ENTER_POWER_OFF	
								;//NOTE.
								;//1) rGSTATUS3 should have the return address after wake-up from POWER_OFF mode.
	
	ldr r0,=REFRESH		
	ldr r1,[r0]		;r1=rREFRESH	
	orr r1, r1, #BIT_SELFREFRESH
	str r1, [r0]				;//Enable SDRAM self-refresh

	mov r1,#16	   				;//Wait until self-refresh is issued,which may not be needed.
0	subs r1,r1,#1
	bne %B0

	ldr 	r1,=MISCCR
	ldr	r0,[r1]
	orr	r0,r0,#(7<<17)  		;//Make sure that SCLK0:SCLK->0, SCLK1:SCLK->0, SCKE=L during boot-up 
	str	r0,[r1]

	ldr r0,=CLKCON
	str r2,[r0]    

	b .							;//CPU will die here.
	

WAKEUP_POWER_OFF
								;//Release SCLKn after wake-up from the POWER_OFF mode.
	ldr 	r1,=MISCCR
	ldr	r0,[r1]
	bic	r0,r0,#(7<<17)  		;//SCLK0:0->SCLK, SCLK1:0->SCLK, SCKE:L->H
	str	r0,[r1]
	
								;//Set memory control registers
    ldr	r0,=SMRDATA
	ldr	r1,=BWSCON				;//BWSCON Address
	add	r2, r0, #52				;//End address of SMRDATA
0       
	ldr	r3, [r0], #4    
	str	r3, [r1], #4    
	cmp	r2, r0		
	bne	%B0

	mov r1,#256
0	subs r1,r1,#1				;//1) wait until the SelfRefresh is released.
	bne %B0	

	ldr r1,=GSTATUS3 			;//GSTATUS3 has the start address just after POWER_OFF wake-up
	ldr r0,[r1]
	mov pc,r0

	LTORG   
HandlerFIQ      HANDLER HandleFIQ
HandlerIRQ      HANDLER HandleIRQ
HandlerUndef    HANDLER HandleUndef
HandlerSWI      HANDLER HandleSWI
HandlerDabort   HANDLER HandleDabort
HandlerPabort   HANDLER HandlePabort



IsrIRQ  
	sub	sp,sp,#4       					;//reserved for PC
	stmfd	sp!,{r8-r9}   
	
	ldr	r9,=INTOFFSET
	ldr	r9,[r9]
	ldr	r8,=HandleEINT0
	add	r8,r8,r9,lsl #2
	ldr	r8,[r8]
	str	r8,[sp,#8]
	ldmfd	sp!,{r8-r9,pc}

;//====================================================================
;// ENTRY  
;//===================================================================
ResetHandler
	ldr	r0,=WTCON       ;//watch dog disable 
	ldr	r1,=0x0         
	str	r1,[r0]

	ldr	r0,=INTMSK
	ldr	r1,=0xffffffff  ;//all interrupt disable
	str	r1,[r0]

	ldr	r0,=INTSUBMSK
	ldr	r1,=0x7ff		;//all sub interrupt disable, 2002/04/10
	str	r1,[r0]

	[ {FALSE}
        ;// rGPFDAT = (rGPFDAT & ~(0xf<<4)) | ((~data & 0xf)<<4);