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📄 44b_isr_s.s

📁 RockOS是在ARM上开发的
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;   Copyright (c) 2006 by RockOS.
;;   All rights reserved.
;;
;;   This software is supported by Rock Software Workroom.
;;
;;   Any bugs please contact the author with e-mail or QQ:
;;     E-mail : baobaoba520@yahoo.com.cn
;;         QQ : 59681888
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;File name   : 44b_isr.s
;;Description : All interrupt service routines are defined in this file.
;;            : 
;;            : 
;;            : 
;;            :
;;Auther      : sunxinqiu
;;History     :
;;  2006-3-15   first release.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

    include 44b.inc

    IMPORT g_cpuIntDepth

    IMPORT g_runningTask
    IMPORT g_runningTcb

    IMPORT OSEnterISR
    IMPORT OSLeaveISR
    IMPORT OSLeaveException

    IMPORT undef_proc
    IMPORT pabort_proc
    IMPORT dabort_proc

    IMPORT OnTick
    IMPORT OnRxD0

    AREA    __isr_text,CODE,READONLY

    EXPORT UndefHandler
UndefHandler
    sub   sp, sp, #4            ;; reserved for PC
    stmfd sp!,{r8}
    ldr   r8, =HandleUndef
    str   r8, [sp, #4]
    ldmfd sp!, {r8, pc}

    EXPORT SwiHandler
SwiHandler
    sub   sp, sp, #4            ;; reserved for PC
    stmfd sp!,{r8}
    ldr   r8, =HandleSwi
    str   r8, [sp, #4]
    ldmfd sp!, {r8, pc}

    EXPORT PabortHandler
PabortHandler
    sub   sp, sp, #4            ;; reserved for PC
    stmfd sp!,{r8}
    ldr   r8, =HandlePabort
    str   r8, [sp, #4]
    ldmfd sp!, {r8, pc}

    EXPORT DabortHandler
DabortHandler
    sub   sp, sp, #4            ;; reserved for PC
    stmfd sp!,{r8}
    ldr   r8, =HandleDabort
    str   r8, [sp, #4]
    ldmfd sp!, {r8, pc}

    EXPORT FiqHandler
FiqHandler
    subs  pc, lr, #4

    EXPORT IrqHandler
IrqHandler
    sub   sp, sp, #4            ;; reserved for PC
    stmfd sp!,{r8-r9}

    ldr r9, =rI_ISPR
    ldr r9, [r9]
    mov r8, #0x0
0   movs r9, r9, lsr #1
    bcs  %F1
    add  r8, r8, #4
    b    %B0
1   ldr  r9, =HandleADC
    add  r9, r9, r8
    ldr  r9, [r9]
    str  r9, [sp, #8]
    ldmfd sp!, {r8-r9,pc}

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;Function    : void OnUndefException(void)
;;Params      : N/A
;;            : 
;;            : 
;;            : 
;;Return      : N/A
;;Description : Undefined instruction exception handler.
;;            : 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
    EXPORT OnUndefException
OnUndefException
    stmfd  sp!, {r0-r12, lr}

    ;; create the register file (the scene when enter Undef mode.)
    stmfd  sp!, {lr}        ;; the scence's PC
    sub    sp, sp, #4       ;; the scence's LR
    sub    sp, sp, #4       ;; the scence's SP
    stmfd  sp!, {r0-r12}    ;; the scence's r0-r12
    mrs    r0, spsr
    stmfd  sp!, {r0}        ;; the scence's CPSR

    ;; change to the scence mode and get the LR and SP.
    mrs    r2, cpsr
    mrs    r0, spsr
    orr    r0, r0, #(NO_INT)
    msr    cpsr_csxf, r0
    mov    r0, sp
    mov    r1, lr
    msr    cpsr_csxf, r2
    str    r0, [sp, #56]
    str    r1, [sp, #60]

    mov    r0, sp
    bl     undef_proc
    add    sp, sp, #64

    ldmfd  sp!, {r0-r12, lr}
    b      OSLeaveException

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;Function    : void OnPabortException(void)
;;Params      : N/A
;;            : 
;;            : 
;;            : 
;;Return      : N/A
;;Description : Prefetch abort exception handler.
;;            : 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
    EXPORT OnPabortException
OnPabortException
    sub    lr, lr, #4
    stmfd  sp!, {r0-r12, lr}

    ;; create the register file (the scene when enter Undef mode.)
    stmfd  sp!, {lr}        ;; the scence's PC
    sub    sp, sp, #4       ;; the scence's LR
    sub    sp, sp, #4       ;; the scence's SP
    stmfd  sp!, {r0-r12}    ;; the scence's r0-r12
    mrs    r0, spsr
    stmfd  sp!, {r0}        ;; the scence's CPSR

    ;; change to the scence mode and get the LR and SP.
    mrs    r2, cpsr
    mrs    r0, spsr
    orr    r0, r0, #(NO_INT)
    msr    cpsr_csxf, r0
    mov    r0, sp
    mov    r1, lr
    msr    cpsr_csxf, r2
    str    r0, [sp, #56]
    str    r1, [sp, #60]

    mov    r0, sp
    bl     pabort_proc
    add    sp, sp, #64

    ldmfd  sp!, {r0-r12, lr}
    b OSLeaveException

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;Function    : void OnDabortException(void)
;;Params      : N/A
;;            : 
;;            : 
;;            : 
;;Return      : N/A
;;Description : Data abort exception handler.
;;            : 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
    EXPORT OnDabortException
OnDabortException
    sub    lr, lr, #8
    stmfd  sp!, {r0-r12, lr}

    ;; create the register file (the scene when enter Undef mode.)
    stmfd  sp!, {lr}        ;; the scence's PC
    sub    sp, sp, #4       ;; the scence's LR
    sub    sp, sp, #4       ;; the scence's SP
    stmfd  sp!, {r0-r12}    ;; the scence's r0-r12
    mrs    r0, spsr
    stmfd  sp!, {r0}        ;; the scence's CPSR

    ;; change to the scence mode and get the LR and SP.
    mrs    r2, cpsr
    mrs    r0, spsr
    orr    r0, r0, #(NO_INT)
    msr    cpsr_csxf, r0
    mov    r0, sp
    mov    r1, lr
    msr    cpsr_csxf, r2
    str    r0, [sp, #56]
    str    r1, [sp, #60]

    mov    r0, sp
    bl     dabort_proc
    add    sp, sp, #64

    ldmfd  sp!, {r0-r12, lr}
    b OSLeaveException

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;Function    : void __irq OnTickInterrupt(void)
;;Params      : N/A
;;            : 
;;            : 
;;            : 
;;Return      : N/A
;;Description : ISR for tick interrupt.
;;            : 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
    EXPORT OnTickInterrupt
OnTickInterrupt
    sub   lr, lr, #4
    stmfd sp!, {r0-r3, lr}
    mrs   r0, spsr
    stmfd sp!, {r0}

    stmfd sp!, {r12, lr}
    bl    OSEnterISR
    ldmfd sp!, {r12, lr}

    cmp   r0, #1                        ;; if (g_cpuIntDepth == 1) {
    bne   %f2
1   mov   r2, lr                        ;;      r2 = PC for the task which is interrupted.
    mov   r3, sp                        ;;      r3 = IRQ stack top
    msr   cpsr_c, #(SVC_MODE|NO_INT)    ;;      change to SVC mode & save task context
    stmfd sp!, {r2}                     ;;      save task's PC to its own stack.
    stmfd sp!, {lr}                     ;;      save task's LR to its own stack.
    stmfd sp!, {r4-r12}
    ldmfd r3!, {r8}                     ;;      get task's CPSR from IRQ's stack
    ldmfd r3!, {r4-r7}                  ;;      save task's {r0-r3} to its own stack
    stmfd sp!, {r4-r7}
    stmfd sp!, {r8}                     ;;      save task's CPSR to its own stack

    ldr   r8, =g_runningTcb             ;;      g_runningTcb->pSP = sp
    ldr   r8, [r8]
    str   sp, [r8]
    msr   cpsr_c, #(IRQ_MODE|NO_INT)    ;;      back to IRQ mode
                                        ;; }
2   stmfd sp!, {r12, lr}                ;;
    bl    OnTick                        ;; OnTick();
    ldmfd sp!, {r12, lr}                ;;

    ldr   r1, =rI_ISPC                  ;; clear the I_ISPR by writing I_ISPC
    ldr   r0, =BIT_TICK
    str   r0, [r1]

    ldr   r1, =g_cpuIntDepth            ;; g_cpuIntDepth--
    ldr   r0, [r1]
    sub   r0, r0, #1
    str   r0, [r1]

    cmp   r0, #0                        ;; if (g_cpuIntDepth == 0)  {
    bne   %f3
    add   sp, sp, #24                   ;;      clear the IRQ stack(task's r0~r3, pc, cpsr)
    msr   cpsr_c, #(SVC_MODE|NO_INT)    ;;      change to SVC mode
    bl    OSLeaveISR                    ;;      OSLeaveISR();
                                        ;; }
3   ldmfd sp!, {r0}                     ;; restore the spsr from IRQ stack
    msr   spsr_cxsf, r0
    ldmfd sp!, {r0-r3, pc}^             ;; return to previous ISR.

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;Function    : void __irq OnTimer5Interrupt(void)
;;Params      : N/A
;;            : 
;;            : 
;;            : 
;;Return      : N/A
;;Description : ISR for tick interrupt.
;;            : 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
    EXPORT OnTimer5Interrupt
OnTimer5Interrupt
    sub   lr, lr, #4
    stmfd sp!, {r0-r3, lr}
    mrs   r0, spsr
    stmfd sp!, {r0}

    stmfd sp!, {r12, lr}
    bl    OSEnterISR
    ldmfd sp!, {r12, lr}

    cmp   r0, #1                        ;; if (g_cpuIntDepth == 1) {
    bne   %f2
1   mov   r2, lr                        ;;      r2 = PC for the task which is interrupted.
    mov   r3, sp                        ;;      r3 = IRQ stack top
    msr   cpsr_c, #(SVC_MODE|NO_INT)    ;;      change to SVC mode & save task context
    stmfd sp!, {r2}                     ;;      save task's PC to its own stack.
    stmfd sp!, {lr}                     ;;      save task's LR to its own stack.
    stmfd sp!, {r4-r12}
    ldmfd r3!, {r8}                     ;;      get task's CPSR from IRQ's stack
    ldmfd r3!, {r4-r7}                  ;;      save task's {r0-r3} to its own stack
    stmfd sp!, {r4-r7}
    stmfd sp!, {r8}                     ;;      save task's CPSR to its own stack

    ldr   r8, =g_runningTcb             ;;      g_runningTcb->pSP = sp
    ldr   r8, [r8]
    str   sp, [r8]
    msr   cpsr_c, #(IRQ_MODE|NO_INT)    ;;      back to IRQ mode
                                        ;; }
2   stmfd sp!, {r12, lr}                ;;
    bl    OnTick                        ;; OnTick();
    ldmfd sp!, {r12, lr}                ;;

    ldr   r1, =rI_ISPC                  ;; clear the I_ISPR by writing I_ISPC
    ldr   r0, =BIT_TIMER5
    str   r0, [r1]

    ldr   r1, =g_cpuIntDepth            ;; g_cpuIntDepth--
    ldr   r0, [r1]
    sub   r0, r0, #1
    str   r0, [r1]

    cmp   r0, #0                        ;; if (g_cpuIntDepth == 0)  {
    bne   %f3
    add   sp, sp, #24                   ;;      clear the IRQ stack(task's r0~r3, pc, cpsr)
    msr   cpsr_c, #(SVC_MODE|NO_INT)    ;;      change to SVC mode
    bl    OSLeaveISR                    ;;      OSLeaveISR();
                                        ;; }
3   ldmfd sp!, {r0}                     ;; restore the spsr from IRQ stack
    msr   spsr_cxsf, r0
    ldmfd sp!, {r0-r3, pc}^             ;; return to previous ISR.

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;Function    : void __irq OnRxD0Interrupt(void)
;;Params      : N/A
;;            : 
;;            : 
;;            : 
;;Return      : N/A
;;Description : ISR for URXD0 interrupt.
;;            : 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
    EXPORT OnRxD0Interrupt
OnRxD0Interrupt
    sub   lr, lr, #4
    stmfd sp!, {r0-r3, lr}
    mrs   r0, spsr
    stmfd sp!, {r0}

    stmfd sp!, {r12, lr}
    bl    OSEnterISR
    ldmfd sp!, {r12, lr}

    cmp   r0, #1                        ;; if (g_cpuIntDepth == 1) {
    bne   %f2
1   mov   r2, lr                        ;;      r2 = PC for the task which is interrupted.
    mov   r3, sp                        ;;      r3 = IRQ stack top
    msr   cpsr_c, #(SVC_MODE|NO_INT)    ;;      change to SVC mode & save task context
    stmfd sp!, {r2}                     ;;      save task's PC to its own stack.
    stmfd sp!, {lr}                     ;;      save task's LR to its own stack.
    stmfd sp!, {r4-r12}
    ldmfd r3!, {r8}                     ;;      get task's CPSR from IRQ's stack
    ldmfd r3!, {r4-r7}                  ;;      save task's {r0-r3} to its own stack
    stmfd sp!, {r4-r7}
    stmfd sp!, {r8}                     ;;      save task's CPSR to its own stack

    ldr   r8, =g_runningTcb             ;;      g_runningTcb->pSP = sp
    ldr   r8, [r8]
    str   sp, [r8]
    msr   cpsr_c, #(IRQ_MODE|NO_INT)    ;;      back to IRQ mode
                                        ;; }
2   stmfd sp!, {r12, lr}                ;;
    bl    OnRxD0                        ;; OnRxD0();
    ldmfd sp!, {r12, lr}                ;; 

    ldr   r1, =rI_ISPC                  ;; clear the I_ISPR by writing I_ISPC
    ldr   r0, =BIT_URXD0
    str   r0, [r1]

    ldr   r1, =g_cpuIntDepth            ;; g_cpuIntDepth--
    ldr   r0, [r1]
    sub   r0, r0, #1
    str   r0, [r1]

    cmp   r0, #0                        ;; if (g_cpuIntDepth == 0)  {
    bne   %f3
    add   sp, sp, #24                   ;;      clear the IRQ stack(task's r0~r3, pc, cpsr)
    msr   cpsr_c, #(SVC_MODE|NO_INT)    ;;      change to SVC mode
    bl    OSLeaveISR                    ;;      OSLeaveISR();
                                        ;; }

3   ldmfd sp!, {r0}                     ;; restore the spsr from IRQ stack
    msr   spsr_cxsf, r0
    ldmfd sp!, {r0-r3, pc}^             ;; return to previous ISR.


    AREA __isr_table, DATA, READWRITE
    ^   _ISR_STARTADDRESS
HandleReset     #   4
HandleUndef     #   4
HandleSwi       #   4
HandlePabort    #   4
HandleDabort    #   4
HandleReserved  #   4
HandleIrq       #   4
HandleFiq       #   4
HandleADC       #   4
HandleRTC       #   4
HandleUTXD1     #   4
HandleUTXD0     #   4
HandleSIO       #   4
HandleIIC       #   4
HandleURXD1     #   4
HandleURXD0     #   4
HandleTIMER5    #   4
HandleTIMER4    #   4
HandleTIMER3    #   4
HandleTIMER2    #   4
HandleTIMER1    #   4
HandleTIMER0    #   4
HandleUERR01    #   4
HandleWDT       #   4
HandleBDMA1     #   4
HandleBDMA0     #   4
HandleZDMA1     #   4
HandleZDMA0     #   4
HandleTICK      #   4
HandleEINT4567  #   4
HandleEINT3     #   4
HandleEINT2     #   4
HandleEINT1     #   4
HandleEINT0     #   4

    END

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