📄 usb_init.c
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/******************************************************************************
*
* (c) copyright Freescale Semiconductor Hong Kong Ltd 2004
* ALL RIGHTS RESERVED
*
*******************************************************************************
** THIS CODE IS ONLY INTENDED AS AN EXAMPLE FOR DEMONSTRATING THE FREESCALE **
** MICROCONTROLLERS. IT HAS ONLY BEEN GIVEN A MIMIMUM LEVEL OF TEST. IT IS **
** PROVIDED 'AS SEEN' WITH NO GUARANTEES AND NO PROMISE OF SUPPORT. **
*******************************************************************************
*
* FILE: usb_init.c REVISION 0.1
*
* DESCRIPTION: This module handles the USB state machine & command processor
* applicaton tasks for the system
*
* NOTES: All modules remain at their reset addresses
*
* UPDATED HISTORY:
*
* REV YYYY.MM.DD AUTHOR DESCRIPTION OF CHANGE
* --- ---------- ------ ---------------------
* 0.0 2003.03.01 Vincent Ko Initial version
* 0.1 2004.04.12 Derek Lau Demo version
*
******************************************************************************/
/* Freescale is not obligated to provide any support, upgrades or new */
/* releases of the Software. Freescale may make changes to the Software at */
/* any time, without any obligation to notify or provide updated versions of */
/* the Software to you. Freescale expressly disclaims any warranty for the */
/* Software. The Software is provided as is, without warranty of any kind, */
/* either express or implied, including, without limitation, the implied */
/* warranties of merchantability, fitness for a particular purpose, or */
/* non-infringement. You assume the entire risk arising out of the use or */
/* performance of the Software, or any systems you design using the software */
/* (if any). Nothing may be construed as a warranty or representation by */
/* Freescale that the Software or any derivative work developed with or */
/* incorporating the Software will be free from infringement of the */
/* intellectual property rights of third parties. In no event will Freescale */
/* be liable, whether in contract, tort, or otherwise, for any incidental, */
/* special, indirect, consequential or punitive damages, including, but not */
/* limited to, damages for any loss of use, loss of time, inconvenience, */
/* commercial loss, or lost profits, savings, or revenues to the full extent */
/* such may be disclaimed by law. The Software is not fault tolerant and is */
/* not designed, manufactured or intended by Freescale for incorporation */
/* into products intended for use or resale in on-line control equipment in */
/* hazardous, dangerous to life or potentially life-threatening environments */
/* requiring fail-safe performance, such as in the operation of nuclear */
/* facilities, aircraft navigation or communication systems, air traffic */
/* control, direct life support machines or weapons systems, in which the */
/* failure of products could lead directly to death, personal injury or */
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/* any derivative work of the Software for High Risk Activities. */
/* Freescale and the Freescale logos are registered trademarks of Freescale */
/* Semiconductor Inc. */
/*****************************************************************************/
#include "FreescaleDef.h" // Get my definitions (Constants & Macros)
#include "UF32reg.h" // Get the UF32 registers.
#include "mk_extern.h" // Get Mini-Kernel global prototypes
//#include "ATA_extern.h"
#include "usb_includes.h" // Get USB module Configuration
#include "usb_extern.h" // Get External variable
// code is placed in the main code area.
#pragma CODE_SEG DEFAULT
//#pragma CODE_SEG CodeForceToPseudo_ROM2
// ===========================================================
// IQUE_Module_Init() -
//
// Enable the IQUE module
//
// ===========================================================
void IQUE_Module_Init(void)
{
IQUECR = (1<<CH34DBE)+(1<<IQUERST)+(1<<IQUEEN); // Enable IQUECR
// QC12DTR = (1<<DTHE)+(1<<DRHE); // Enable force handshake
QC34DTR = (1<<DTHE)+(1<<DRHE); // Enable force handshake
};
// ===========================================================
// USB_ModuleInit() -
//
// Enable the USB module
//
// ===========================================================
void USB_ModuleInit(void)
{
mSetBit(MCE, UMCR); // Enable Module Clock
// UMCR = 0x4002; // bit 11-Normal PHY operation
UMCRL = 0x02; // bit 11-Normal PHY operation
// bit 4-SET_DESCRIPTOR not supported
// bit 3-High speed
// bit 2-Remote Wakeup supported
// bit 1-self powered device
// bit 0-SYNC_FRAME command not supported
// while (mCheckBit(LOCK,CRGFLG)==0x00);
// mSetBit(PLLSEL, CLKSEL); // Select PHY clock as system clock
UMSR1 = (1<<USSC) + (1<<URSC);
UIMR = 0x3801; // bit0 Enable SETUPIE
// bit1 Enable SETOVRIE
// bit2 Enable SOFIE
// bit11 Enable URSCIE
// bit12 Disable USSCIE
// bit13 Enable SETECRIE
// mClearBit(RESUMEIE, UIMR); // Make sure resume interrupt mask is off
// PORTT = 0x00; // Initialise PTI
// DDRT = 0x0f; // Put PTI to outpu t
// mSetBit(ON_LED, PORTT); // Put light LED
};
//#pragma CODE_SEG DEFAULT
// ===========================================================
// USB_InitCBITransport() -
//
// Configurate 1 x 512 bytes BULK in, 1 x 512 Bytes BULK out
// and 1 x 2 bytes interrupt endpoint.
//
// ===========================================================
/*
void USB_InitCBITransport(void) {
// Support Single Configuration and Single Interface
UEPCSELR_h = 0x08; // config UNCIR
UNCIR_h = 0x0000;
UNCIR_l = 0x0011;
// Support No Alternative Setting
UEPCSELR_h = 0x09; // config UNASR
UNASR_h = 0x0000;
UNASR_l = 0x0000;
// Physical Endpoint # 1 - Control
UEPCSELR_h = 0x01; // config physical endpoint 1
UPECFGR_h = 0x0200; // packet size = 64
UPECFGR_l = 0x0000; // Alternate setting = 0
// Interface = 0
// Configuration = 0
// Type = control
// Dir = IO
// EPnum = 0
UEPCSR0 = 0x3000; // Clear DVALID, Clear TFRC, Enable TCIE
UEPCSR1 = 0x3000; // Clear DVALID, Clear TFRC, Enable TCIE
// Physical Endpoint # 5 - BULK IN with 512 byte buffer
UEPCSELR_h = 0x05;
UPECFGR_h = 0x1000; // packet size = 512
UPECFGR_l = 0x00d1; // Alternate setting = 0
// Interface = 0
// Configuration = 1
// Type = BULK
// Dir = IN
// EPnum = 1
UEPCSR5A = 0x7800; // Clear DVALID, Enable NACK, Clear TFRC, Enable TCIE
UEPCSR5B = 0x1000; // Enable TERRIE
// Setup QUE Channel 2 for BULK OUT endpoint
QC3CR = 0xb4; // Q2VIE enable
// Q2FIE enable
// Q2EN enable
// 256 block size
// 16 bit transfer
// No passthrough
QC3SZB = 0x12; // 2 block of 256 bytes
// Base at %0010 offset
QC3REQ = 0x01; // Channel 3 set to USB TX
EP_Resource[Config1][EndPt1] = PHY5; // Set QUE Buffer 1 for Config1 EP1
// Physical Endpoint # 4 - BULK OUT with 512 byte buffer
UEPCSELR_h = 0x04;
UPECFGR_h = 0x1000; // packet size = 512
UPECFGR_l = 0x00c2; // Alternate setting = 0
// Interface = 0
// Configuration = 1
// Type = BULK
// Dir = OUT
// EPnum = 2
UEPCSR4A = 0x3800; // Clear DVALID, Clear TFRC, Enable TCIE
UEPCSR4B = 0x1000; // Enable TERRIE
// Setup QUE Channel 1 for BULK OUT endpoint
QC1CR = 0xb4; // Q1VIE enable
// Q1FIE enable
// Q1EN enable
// No passthrough
// 256 block size
// 16 bit transfer
// No passthrough
QC1SZB = 0x10; // 2 block of 256 bytes
// Base at %0000 offset
QC1REQ = 0x00; // Channel 1 set to USB RX
EP_Resource[Config1][EndPt2] = PHY4; // Set QUE Buffer 1 for Config1 EP2
// Physical Endpoint # 2 - INTERRUPT IN with 2 byte buffer
UEPCSELR_h = 0x02;
UPECFGR_h = 0x0010; // packet size = 2
UPECFGR_l = 0x00f3; // Alternate setting = 0
// Interface = 0
// Configuration = 1
// Type = INTERRUPT
// Dir = IN
// EPnum = 3
EP_Resource[Config1][EndPt3] = PHY2; // Set Physical Endpoint 2 for Config1 EP3
UEPCSR2 = 0x3000; // Clear DVALID, Clear TFRC, Enable TCIE
};
*/
// ===========================================================
// USB_InitBulkOnlyTransport() -
//
// Configurate 1 x 64 bytes BULK in and 1 x 64 Bytes BULK out.
//
// ===========================================================
void USB_InitBulkOnlyTransport(void)
{
if (gUSBFullSpeed)
gUSBPacketSize = 32; // 32 word
else
gUSBPacketSize = 256; // 256 word
// Support Single Configuration and Single Interface
UEPCSELR_h = 0x08; // config UNCIR
UNCIR_h = 0x0000;
UNCIR_l = 0x0011;
// Support No Alternative Setting
UEPCSELR_h = 0x09; // config UNASR
UNASR_h = 0x0000;
UNASR_l = 0x0000;
// Physical Endpoint # 1 - Control
UEPCSELR_h = 0x01; // config physical endpoint 1
UPECFGR_h = 0x0200; // packet size = 64
UPECFGR_l = 0x0000; // Alternate setting = 0
// Interface = 0
// Configuration = 0
// Type = control
// Dir = IO
// EPnum = 0
UEPCSR0 = 0x3000; // Clear DVALID, Clear TFRC, Enable TCIE
UEPCSR1 = 0x3000; // Clear DVALID, Clear TFRC, Enable TCIE
UEPCSR5A = 0x7800; // Enable SNACK, Clear TFRC, Enable TCIE
UEPCSR5B = 0x0000; // Disable TERRIE
// Setup QUE Channel 2 for BULK IN endpoint
if (gUSBFullSpeed)
{
UEPCSELR_h = 0x05; // Physical EP5 (IN)
UPECFGR_h = 0x8200; // packet size = 64
UPECFGR_l = 0x00d1; // Alternate setting = 0
// Interface = 0
// Configuration = 1
// Type = BULK
// Dir = IN
// EPnum = 1
QC3CR = (1<<QnEN)+(1<<QnSML)+(1<<Qn16EN)+(1<<QnPRST);
// Q3VIE disable
// Q3FIE disable
// Q3EN enable
// 256 bytes block size
// 16 bit transfer
// passthrough mode
QC3SZB = 0x3f; // 4 block of 16 bytes (FS), base 0x20f0
UEPCSELR_h = 0x04; // Physical EP4 (OUT)
UPECFGR_h = 0x8200; // packet size = 64
UPECFGR_l = 0x00c1; // Alternate setting = 0
// Interface = 0
// Configuration = 1
// Type = BULK
// Dir = OUT
QC1CR = (1<<QnEN)+(1<<QnSML)+(1<<Qn16EN)+(1<<QnPRST);
QC1SZB = 0x30; // 4 block of 16 bytes (FS), base 0x2000
}
else
{
UEPCSELR_h = 0x05; // Physical EP5 (IN)
UPECFGR_h = 0x9000; // packet size = 512
UPECFGR_l = 0x00d1; // Alternate setting = 0
// Interface = 0
// Configuration = 1
// Type = BULK
// Dir = IN
// EPnum = 1
QC3CR = (1<<QnEN)+(1<<Qn16EN)+(1<<QnPRST);
// Q3VIE disable
// Q3FIE disable
// Q3EN enable
// 256 bytes block size
// 16 bit transfer
// passthrough mode
QC3SZB = 0x12; // 2 block 0f 256 bytes (HS), base 0x2000
UEPCSELR_h = 0x04; // Physical EP4 (IN)
UPECFGR_h = 0x9000; // packet size = 512
UPECFGR_l = 0x00c1; // Alternate setting = 0
QC1CR = (1<<QnEN)+(1<<Qn16EN)+(1<<QnPRST);
QC1SZB = 0x10; // 2 block of 256 bytes (HS)
}
QC3REQ = 0x01; // Channel 3 set to USB TX
EP_Resource[Config1][EndPt1] = PHY5; // Set QUE Buffer 1 for Config1 EP1
do
UEPCSR4A = (1<<TFRC)+(1<<USBTCIE)+(1<<CTERR); // Clear DVALID, Clear TFRC, Enable TCIE
while (UEPCSR4A != (1<<USBTCIE)+(1<<CTERR));
UEPCSR4B = (1<<USBTERRIE); // Enable SPKTIE, TERRIE
QC1REQ = 0x00; // Channel 1 set to USB RX
EP_Resource[Config1][EndPt2] = PHY4; // Set QUE Buffer 1 for Config1 EP2
};
//
// The end of file usb_init.c
// *********************************************************************************⌨️ 快捷键说明
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