📄 s2410.h
字号:
//
// Copyright (c) Microsoft Corporation. All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
/*++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.
Copyright (c) 2001. Samsung Electronics, co. ltd All rights reserved.
Module Name:
Abstract:
ARM920(S3C2410) definitions
rev:
2002.5.20 : add define CE_MAJOR_VER == 0x0004 for CE.Net by pcj ( bestworld@samsung.com )
2002.5.16 : change OEM_CLOCK_FREQ value for Audio ( bestworld@samsung.com )
2002.4.3 : S3C2410 Support (SOC)
2002.1.29 : change Timer values
2002.1.29 : CE.NET port
2002.1.22 : Add USBD definitions (kwangyoon LEE, kwangyoon@samsung.com)
Notes:
--*/
#define ARM920
// Board timer constants.
//
#define S2410FCLK (203 * 1000 * 1000) // 203MHz (FCLK).
#define PCLKDIV 4 // P-clock (PCLK) divisor.
#define S2410PCLK (S2410FCLK / PCLKDIV) // PCLK.
#define S2410UCLK 50331648 // 48MHz - for serial UARTs.
#define PRESCALER 200
#define D1_2 0x0
#define D1_4 0x1
#define D1_8 0x2
#define D1_16 0x3
#define D2 2
#define D4 4
#define D8 8
#define D16 16
#define SYS_TIMER_DIVIDER D4
#define OEM_CLOCK_FREQ (S2410PCLK / PRESCALER / SYS_TIMER_DIVIDER)
#define OEM_COUNT_1MS (OEM_CLOCK_FREQ / 1000) // Timer count for 1ms.
#define RESCHED_PERIOD 1 // Reschedule period in ms.
#define RESCHED_INCREMENT (RESCHED_PERIOD * OEM_COUNT_1MS) // Number of ticks per reschedule period.
// Define LCD type of S3C2400X01
#define STN8BPP 1
#define TFT16BPP 2
#define LCDTYPE TFT16BPP // define LCD type as upper definition.
#define AUDIO_CODEC_CLOCK 384
#if (S2410FCLK == 112800000)
#define AUDIO_CODEC_CLOCK 256
#else
#define AUDIO_CODEC_CLOCK 384
#endif
// by pcj for ce.net power management.
#define CE_MAJOR_VER 0x0004
//=======================================================================
// Define S3C2410 Special Registers
//=======================================================================
#ifndef __2410X_H__
#define __2410X_H__
#define CS8900DBG_IOBASE (0xa7000300)
#define CS8900DBG_MEMBASE (0xa6000000)
#define CS8900DBG_IP ((165 << 0) | (213 << 8) | (172 << 16) | (102 << 24))
#define CS8900DBG_MASK ((255 << 0) | (255 << 8) | (255 << 16) | (0 << 24))
#define CS8900DBG_MAC0 0x22
#define CS8900DBG_MAC1 0x33
#define CS8900DBG_MAC2 0x44
#define CS8900DBG_MAC3 0x55
#define CS8900DBG_MAC4 0x66
#define CS8900DBG_MAC5 0x77
#define CS8900DBG_USHORT(l, h) (l | (h << 8))
/*
* Registers : NAND Controller
*/
#define NAND_BASE 0xB0E00000 /* 0x4E000000 */
typedef struct
{
unsigned int rNFCONF; /* 0x00 */
unsigned char rNFCMD; /* 0x04 */
unsigned char d0[3];
unsigned char rNFADDR; /* 0x08 */
unsigned char d1[3];
unsigned char rNFDATA; /* 0x0c */
unsigned char d2[3];
unsigned int rNFSTAT; /* 0x10 */
unsigned char rNFECC0; /* 0x14 */
unsigned char rNFECC1; /* 0x15 */
unsigned char rNFECC2; /* 0x16 */
} NANDreg;
//
// Memory Controller Register
//
#define MEMCTRL_BASE 0xB0800000 // 0x49000000
typedef struct {
unsigned long rBWSCON; // 0
unsigned long rBANKCON0; // 4
unsigned long rBANKCON1; // 8
unsigned long rBANKCON2; // c
unsigned long rBANKCON3; // 10
unsigned long rBANKCON4; // 1c
unsigned long rBANKCON5; // 18
unsigned long rBANKCON6; // 1c
unsigned long rBANKCON7; // 20
unsigned long rREFRESH; // 24
unsigned long rBANKSIZE; // 28
unsigned long rMRSRB6; // 2c
unsigned long rMRSRB7; // 30
}MEMreg;
//
// Clock & Power Management Special Register
#define CLKPWR_BASE 0xB0C00000 // 0x4C000000
typedef struct {
unsigned long rLOCKTIME;
unsigned long rMPLLCON;
unsigned long rUPLLCON;
unsigned long rCLKCON;
unsigned long rCLKSLOW;
unsigned long rCLKDIVN;
}CLKPWRreg;
//
// DMA Register
//
#define FRAMEBUF_BASE (DMA_BUFFER_BASE + 0x00100000)
#define FRAMEBUF_DMA_BASE (0x30000000 + 0x00100000)
#define DMA_BASE 0xB0B00000 // 0x4B0000000
typedef struct {
unsigned int rDISRC0; // 00
unsigned int rDISRCC0; // 04
unsigned int rDIDST0; // 08
unsigned int rDIDSTC0; // 0C
unsigned int rDCON0; // 10
unsigned int rDSTAT0; // 14
unsigned int rDCSRC0; // 18
unsigned int rDCDST0; // 1C
unsigned int rDMASKTRIG0; // 20
unsigned int rPAD1[7]; // 24 - 3C
unsigned int rDISRC1; // 40
unsigned int rDISRCC1; // 44
unsigned int rDIDST1; // 48
unsigned int rDIDSTC1; // 4C
unsigned int rDCON1; // 50
unsigned int rDSTAT1; // 54
unsigned int rDCSRC1; // 58
unsigned int rDCDST1; // 5C
unsigned int rDMASKTRIG1; // 60
unsigned int rPAD2[7]; // 64 - 7C
unsigned int rDISRC2; // 80
unsigned int rDISRCC2; // 84
unsigned int rDIDST2; // 88
unsigned int rDIDSTC2; // 8C
unsigned int rDCON2; // 90
unsigned int rDSTAT2; // 94
unsigned int rDCSRC2; // 98
unsigned int rDCDST2; // 9C
unsigned int rDMASKTRIG2; // A0
unsigned int rPAD3[7]; // A4 - BC
unsigned int rDISRC3; // C0
unsigned int rDISRCC3; // C4
unsigned int rDIDST3; // C8
unsigned int rDIDSTC3; // CC
unsigned int rDCON3; // D0
unsigned int rDSTAT3; // D4
unsigned int rDCSRC3; // D8
unsigned int rDCDST3; // DC
unsigned int rDMASKTRIG3; // E0
}DMAreg;
//
// Registers : I/O port
//
#define IOP_BASE 0xB1600000 // 0x56000000
typedef struct {
unsigned int rGPACON; // 00
unsigned int rGPADAT;
unsigned int rPAD1[2];
unsigned int rGPBCON; // 10
unsigned int rGPBDAT;
unsigned int rGPBUP;
unsigned int rPAD2;
unsigned int rGPCCON; // 20
unsigned int rGPCDAT;
unsigned int rGPCUP;
unsigned int rPAD3;
unsigned int rGPDCON; // 30
unsigned int rGPDDAT;
unsigned int rGPDUP;
unsigned int rPAD4;
unsigned int rGPECON; // 40
unsigned int rGPEDAT;
unsigned int rGPEUP;
unsigned int rPAD5;
unsigned int rGPFCON; // 50
unsigned int rGPFDAT;
unsigned int rGPFUP;
unsigned int rPAD6;
unsigned int rGPGCON; // 60
unsigned int rGPGDAT;
unsigned int rGPGUP;
unsigned int rPAD7;
unsigned int rGPHCON; // 70
unsigned int rGPHDAT;
unsigned int rGPHUP;
unsigned int rPAD8;
unsigned int rMISCCR; // 80
unsigned int rDCKCON;
unsigned int rEXTINT0;
unsigned int rEXTINT1;
unsigned int rEXTINT2; // 90
unsigned int rEINTFLT0;
unsigned int rEINTFLT1;
unsigned int rEINTFLT2;
unsigned int rEINTFLT3; // A0
unsigned int rEINTMASK;
unsigned int rEINTPEND;
unsigned int rGSTATUS0;
unsigned int rGSTATUS1; // B0
}IOPreg;
//
// Registers : PWM
//
#define PWM_BASE 0xB1100000 // 0x51000000
typedef struct {
unsigned int rTCFG0;
unsigned int rTCFG1;
unsigned int rTCON;
unsigned int rTCNTB0;
unsigned int rTCMPB0;
unsigned int rTCNTO0;
unsigned int rTCNTB1;
unsigned int rTCMPB1;
unsigned int rTCNTO1;
unsigned int rTCNTB2;
unsigned int rTCMPB2;
unsigned int rTCNTO2;
unsigned int rTCNTB3;
unsigned int rTCMPB3;
unsigned int rTCNTO3;
unsigned int rTCNTB4;
unsigned int rTCNTO4;
}PWMreg ;
//
// Registers : UART
//
#define UART0_BASE 0xB1000000 // 0x50000000
#define UART1_BASE 0xB1004000
#define UART2_BASE 0xB1008000
typedef struct {
unsigned int rULCON;
unsigned int rUCON;
unsigned int rUFCON;
unsigned int rUMCON;
unsigned int rUTRSTAT;
unsigned int rUERSTAT;
unsigned int rUFSTAT;
unsigned int rUMSTAT;
unsigned int rUTXH;
unsigned int rURXH;
unsigned int rUBRDIV;
}UART0reg, UART1reg, UART2reg, UARTreg, S2410_UART_REG, *PS2410_UART_REG;
// 2410 USB DEVICE Function (Written by Seung-han, Lim)
// Little-Endian
struct udcFARBits { // function address reg
BYTE func_addr :7; // function_address
BYTE addr_up :1; // addr_update
};
struct PMRBits { // power management reg
BYTE sus_en :1; // suspend_en
BYTE sus_mo :1; // suspend_mode
BYTE muc_res :1; // mcu_resume
BYTE usb_re :1; // usb_reset
BYTE rsvd1 :3;
BYTE iso_up :1; // iso_update
};
struct EIRBits { // ep interrupt reg
BYTE ep0_int :1; // ep0_interrupt
BYTE ep1_int :1; // ep1_interrupt
BYTE ep2_int :1; // ep2_interrupt
BYTE ep3_int :1; // ep3_interrupt
BYTE ep4_int :1; // ep4_interrupt
BYTE rsvd0 :3;
};
struct UIRBits { // usb interrupt reg
BYTE sus_int :1; // suspend inaterrupt
BYTE resume_int :1; // resume interrupt
BYTE reset_int :1; // reset interrupt
BYTE rsvd0 :5;
};
struct EIERBits { // interrupt mask reg
BYTE ep0_int_en :1; // ep1_int_reg
BYTE ep1_int_en :1; // ep1_int_reg
BYTE ep2_int_en :1; // ep2_int_reg
BYTE ep3_int_en :1; // ep3_int_reg
BYTE ep4_int_en :1; // ep4_int_reg
BYTE rsvd0 :3;
};
struct UIERBits {
BYTE sus_int_en :1; // suspend_int_en
BYTE rsvd1 :1;
BYTE reset_int_en :1; // reset_enable_reg
BYTE rsvd0 :5;
};
struct FNR1Bits { // frame number1 register
BYTE fr_n1 :8; // frame_num1_reg
};
struct FNR2Bits { // frame number2 register
BYTE fr_n2 :8; // frame_num2_reg
};
struct INDEXBits { // index register
BYTE index :8; // index_reg
};
struct EP0ICSR1Bits // EP0 & ICSR1 shared
{
BYTE opr_ipr :1;
BYTE ipr_ :1;
BYTE sts_ur :1;
BYTE de_ff :1;
BYTE se_sds :1;
BYTE sds_sts :1;
BYTE sopr_cdt :1;
BYTE sse_ :1;
};
struct ICSR2Bits { // in csr2 areg
BYTE rsvd1 :4;
BYTE in_dma_int_en :1; // in_dma_int_en
BYTE mode_in :1; // mode_in
BYTE iso :1; // iso/bulk mode
BYTE auto_set :1; // auto_set
};
struct OCSR1Bits { // out csr1 reg
BYTE out_pkt_rdy :1; // out packet reday
BYTE rsvd1 :1;
BYTE ov_run :1; // over_run
BYTE data_error :1; // data_error
BYTE fifo_flush :1; // fifo_flush
BYTE send_stall :1; // send_stall
BYTE sent_stall :1; // sent_stall
BYTE clr_data_tog :1; // clear data toggle
};
struct OCSR2Bits { // out csr2 reg
BYTE rsvd1 :5;
BYTE out_dma_int_en :1; // out_dma_int_en
BYTE iso :1; // iso/bulk mode
BYTE auto_clr :1; // auto_clr
};
struct EP0FBits { // ep0 fifo reg
BYTE fifo_data :8; // fifo data
};
struct EP1FBits { // ep0 fifo reg
BYTE fifo_data :8; // fifo data
};
struct EP2FBits { // ep0 fifo reg
BYTE fifo_data :8; // fifo data
};
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -