cfnand.h

此压缩包为杰得开发得z228的BSP的源代码,可以实现很多功能,尤其是视频解码有很好的效果.

/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.
Copyright (c) 2001  Microsoft Corporation

Module Name:	S3C2440.H

Abstract:		FLASH Media Driver Interface Samsung S3C2440 CPU with NAND Flash 
                controller.
  
Environment:	As noted, this media driver works on behalf of the FAL to directly
				access the underlying FLASH hardware.  Consquently, this module 
				needs to be linked with FLASHFAL.LIB to produce the device driver 
				named FLASHDRV.DLL.

-----------------------------------------------------------------------------*/
#ifndef _S3C2440_DEVBOARD_
#define _S3C2440_DEVBOARD_

//#include "nand.h"
//#include "nanflashfun.h"

//#define S512	//define for 512 byte per Sector
//#define CE_2	//define for 2-chip-select
//#define DATA4

typedef struct
{
	unsigned int  chipid;
	unsigned char chipname[12];
	unsigned char vendor[12];	
	unsigned int  blocknum;		
	unsigned int  pageperblock;	
	unsigned int  sectorperpage;	
	unsigned int  coladdrcycle;
	unsigned int  rowaddrcycle;	
	unsigned int  csnum;
	unsigned int  badpos;		//Offset in oob buffer	
		
	unsigned int  blksize;
	unsigned int  pagesize;
	unsigned int  oobsize;
}NAND_CHIP_INFO;

static NAND_CHIP_INFO ChipInfoList[] = {	
/****************************************************************************************************
 *chipid chipname vendor blocknum pageperblock sectorperpage coladdrcycle rowaddrcycle csnum badpos* 
****************************************************************************************************/
  {0xEC75,"K9F5608U0A","Samsung",2048, 32, 1, 1, 2, 1, 5, 0x04000, 0x200, 0x10},
  {0xEC76,"K9F1208U0A","Samsung",4096, 32, 1, 1, 3, 1, 5, 0x04000, 0x200, 0x10},
  {0xECF1,"K9F1G08U0A","Samsung",1024, 64, 4, 2, 2, 1, 0, 0x20000, 0x800, 0x40},
#ifdef S512  
  {0xECD3,"K9K8G08U0A","Samsung",8192, 256, 4, 2, 3, 1, 0, 0x20000, 0x200, 0x10},
  {0xECDC,"K9K4G08U0M","Samsung",4096, 256, 4, 2, 3, 1, 0, 0x20000, 0x200, 0x10},
#else
  {0xECD3,"K9K8G08U0A","Samsung",8192, 64, 4, 2, 3, 1, 0, 0x20000, 0x800, 0x40},
  {0xECDC,"K9K4G08U0M","Samsung",4096, 64, 4, 2, 3, 1, 0, 0x20000, 0x800, 0x40},  
#endif  
  {0x0000,"NULL","NULL",0,0,0,0,0,0,0,0,0,0}
};

#define CMD_READ                0x00        //  Read
#define CMD_READ1               0x01        //  Read1
#define CMD_READ2               0x50        //  Read2
#define CMD_READ3               0x30        //  Read3
#define CMD_READID              0x90        //  ReadID
#define CMD_WRITE               0x80        //  Write phase 1
#define CMD_WRITE2              0x10        //  Write phase 2
#define CMD_ERASE               0x60        //  Erase phase 1
#define CMD_ERASE2              0xd0        //  Erase phase 2
#define CMD_STATUS              0x70        //  Status read
#define CMD_RDI                 0x85        //  Random Data Input
#define CMD_RDO                 0x05        //  Random Data Output
#define CMD_RDO2                0xE0        //  Random Data Output
#define CMD_RESET               0xff        //  Reset
#define CMD_READ_ID             0x90		    // Read ID

//  Status bit pattern
#define STATUS_READY            0x40        //  Ready
#define STATUS_ERROR            0x01        //  Error
#define	STATUS_ILLACC			      0x08		    //	Illigar Access

//  Use Macros here to avoid extra over head for c function calls
#define READ_REGISTER_BYTE(p)		    (*(PBYTE)(p))
#define WRITE_REGISTER_BYTE(p, v)	  (*(PBYTE)(p)) = (v)
#define READ_REGISTER_USHORT(p)		  (*(PUSHORT)(p))
#define WRITE_REGISTER_USHORT(p, v)	(*(PUSHORT)(p)) = (v)
#define READ_REGISTER_ULONG(p)		  (*(PULONG)(p))
#define WRITE_REGISTER_ULONG(p, v)	(*(PULONG)(p)) = (v)

//  Status bit pattern
#define STATUS_READY		0x40
#define STATUS_ERROR		0x01

// HCLK=133Mhz
#define TACLS		  0
#define TWRPH0		6
#define TWRPH1		2

//  MACROS
#define NF_CE_L()	EnableNandCE//WriteGPio8( 0x08 , 0x0 )	/* enable nandflash CE PIN */
#define NF_CE_L_2()	EnableNandCE2

#define NF_CE_H()	DisableNandCE
#define NF_CE_H_2()	DisableNandCE2

#define NF_CMD(cmd)		WriteReg (CLE, cmd)
#define NF_ADDR(addr)	  WriteReg (ALE, addr)

#define NF_DATA_R()		ReadReg (0x0)
#define NF_DATA_R4()		ReadReg32 (0x0)

#define NF_DATA_W(val)	WriteReg (0x0,  val)
#define NF_DATA_W4(val)	WriteReg32 (0x0,  val)

#define NF_CLEAR_RB()		  while( !(ReadGPioRB(1<<RB_GP_pin)) )	// is flash busy? wait
#define NF_DETECT_RB()		while( !(ReadGPioRB(1<<RB_GP_pin)) )


#define	CLE			(0X400000)
#define ALE			(0X800000)

#define DisableNandCE	WriteGPioCE( (1<<CS_GP_pin)<<2, 1<<CS_GP_pin)    /* disable nandflash CE PIN */
#define EnableNandCE	WriteGPioCE( (1<<CS_GP_pin)<<2, 0x0 )    		/* enable nandflash CE PIN */

#define DisableNandCE2	WriteGPioCE( 0x10 , 1<<CS_GP_pin )    /* disable nandflash CE2 PIN */
#define EnableNandCE2	WriteGPioCE( 0x10 , 0x0 )    /* enable nandflash CE2 PIN */

#endif _S3C2440_DEVBOARD_