67300.h

此压缩包为杰得开发得z228的BSP的源代码,可以实现很多功能,尤其是视频解码有很好的效果.

#define ASSERT_J                                             0x0001 /* Assert J state on selected ports */
#define ASSERT_K                                             0x0000 /* Assert K state on selected ports */

/*********************************************************/
/* MEMORY DIAGNOSTIC REGISTER [W]                        */
/*********************************************************/

#define MEM_DIAG_REG                                         0xC03E /* Memory Diagnostic Register [W] */

/* FIELDS */

#define FAST_REFRESH_EN                                      0x8000 /* Fast Refresh Enable (15x acceleration) */
#define MEM_ARB_SEL                                          0x0700 /* Memory Arbitration */
#define MONITOR_EN                                           0x0001 /* Monitor Enable (Echoes internal address bus externally) */

/* MEMORY ARBITRATION SELECT FIELD VALUES */
#define MEM_ARB_7                                            0x0700 /* Number of dead cycles out of 8 possible */
#define MEM_ARB_6                                            0x0600 /* Should not use any cycle >= 6 */
#define MEM_ARB_5                                            0x0500 /*  */
#define MEM_ARB_4                                            0x0400 /* */
#define MEM_ARB_3                                            0x0300 /* */
#define MEM_ARB_2                                            0x0200 /* */
#define MEM_ARB_1                                            0x0100 /*  */
#define MEM_ARB_0                                            0x0000 /* Power up default */

/*********************************************************/
/* EXTENDED PAGE n MAP REGISTER [R/W]                    */
/*********************************************************/

#define PG1_MAP_REG                                          0xC018 /* Page 1 Map Register [R/W] */
#define PG2_MAP_REG                                          0xC01A /* Page 2 Map Register [R/W] */

/*********************************************************/
/* DRAM CONTROL REGISTER [R/W]                           */
/*********************************************************/

#define DRAM_CTL_REG                                         0xC038 /* DRAM Control Register [R/W] */

/* FIELDS */

#define DRAM_DIS                                             0x0008 /* DRAM Disable */
#define TURBO_EN                                             0x0004 /* Turbo Mode */
#define PAGE_MODE_EN                                         0x0002 /* Page Mode */
#define REFRESH_EN                                           0x0001 /* Refresh  */

/*********************************************************/
/* EXTERNAL MEMORY CONTROL REGISTER [R/W]                */
/*********************************************************/

#define XMEM_CTL_REG                                         0xC03A /* External Memory Control Register [R/W] */
#define X_MEM_CNTRL                                          0xC03A /* Alias for BIOS code */

#define XRAM_BEGIN                                           0x4000 /* External SRAM begin */
#define XROM_BEGIN                                           0xC100 /* External ROM Begin */
#define IROM_BEGIN                                           0xE000 /* Internal ROM Begin */


/* FIELDS */
#define XRAM_MERGE_EN                                        0x2000 /* Overlay XRAMSEL w/ XMEMSEL */
#define XROM_MERGE_EN                                        0x1000 /* Overlay XROMSEL w/ XMEMSEL */
#define XMEM_WIDTH_SEL                                       0x0800 /* External MEM Width Select */
#define XMEM_WAIT_SEL                                        0x0700 /* Number of Extended Memory wait states (0-7) */
#define XROM_WIDTH_SEL                                       0x0080 /* External ROM Width Select */
#define XROM_WAIT_SEL                                        0x0070 /* Number of External ROM wait states (0-7) */
#define XRAM_WIDTH_SEL                                       0x0008 /* External RAM Width Select */
#define XRAM_WAIT_SEL                                        0x0007 /* Number of External RAM wait states (0-7) */

/* XMEM_WIDTH FIELD VALUES */

#define XMEM_8                                               0x0800 /*  */
#define XMEM_16                                              0x0000 /*  */

/* XRAM_WIDTH FIELD VALUES */

#define XROM_8                                               0x0080 /*  */
#define XROM_16                                              0x0000 /*  */

/* XRAM_WIDTH FIELD VALUES */

#define XRAM_8                                               0x0008 /*  */
#define XRAM_16                                              0x0000 /*  */


/*********************************************************/
/* WATCHDOG TIMER REGISTER [R/W]                         */
/*********************************************************/

#define WDT_REG                                              0xC00C /* Watchdog Timer Register [R/W] */

/* FIELDS */

#define WDT_TIMEOUT_FLG                                      0x0020 /* WDT timeout flag */
#define WDT_PERIOD_SEL                                       0x0018 /* WDT period select (options below) */
#define WDT_LOCK_EN                                          0x0004 /* WDT enable */
#define WDT_EN                                               0x0002 /* WDT lock enable */
#define WDT_RST_STB                                          0x0001 /* WDT reset Strobe */

/* WATCHDOG PERIOD FIELD VALUES */

#define WDT_64MS                                             0x0003 /* 64.38 ms */
#define WDT_21MS                                             0x0002 /* 21.68 ms */
#define WDT_5MS                                              0x0001 /* 5.67 ms */
#define WDT_1MS                                              0x0000 /* 1.67 ms */

/*********************************************************/
/* TIMER n REGISTER [R/W]                                */
/*********************************************************/

#define TMR0_REG                                             0xC010 /* Timer 0 Register [R/W] */
#define TIMER_0                                              0xC010 /* Alias for BIOS code */
#define TMR1_REG                                             0xC012 /* Timer 1 Register [R/W] */
#define TIMER_1                                              0xC012 /* Alias for BIOS code */

/*********************************************************/
/*********************************************************/
/* USB REGISTERS                                         */
/*********************************************************/
/*********************************************************/

/*********************************************************/
/* USB n CONTROL REGISTERS [R/W]                         */
/*********************************************************/

#define USB1_CTL_REG                                         0xC08A /* USB 1 Control Register [R/W] */
#define SIE1_USB_CONTROL                                     0xC08A

#define USB2_CTL_REG                                         0xC0AA /* USB 2 Control Register [R/W] */
#define SIE2_USB_CONTROL                                     0xC0AA

/* FIELDS */
#define B_DP_STAT                                            0x8000 /* Port B D+ status */
#define B_DM_STAT                                            0x4000 /* Port B D- status */
#define A_DP_STAT                                            0x2000 /* Port A D+ status */
#define A_DM_STAT                                            0x1000 /* Port A D- status */
#define B_SPEED_SEL                                          0x0800 /* Port B Speed select (See below) */
#define A_SPEED_SEL                                          0x0400 /* Port A Speed select (See below) */
#define MODE_SEL                                             0x0200 /* Mode (See below) */
#define B_RES_EN                                             0x0100 /* Port B Resistors enable */
#define A_RES_EN                                             0x0080 /* Port A Resistors enable */
#define B_FORCE_SEL                                          0x0060 /* Port B Force D+/- state (See below) */
#define A_FORCE_SEL                                          0x0018 /* Port A Force D+/- state (See below) */
#define SUSP_EN                                              0x0004 /* Suspend enable */
#define B_SOF_EOP_EN                                         0x0002 /* Port B SOF/EOP enable */
#define A_SOF_EOP_EN                                         0x0001 /* Port A SOF/EOP enable */


/* USB Control Register1 (0xC08A/0xC0AA) bit mask         */
#define bmHOST_CTL1_SOF0                                     0x0001
#define bmHOST_CTL1_SOF1                                     0x0002
#define bmHOST_CTL1_SUSPEND                                  0x0004
#define bmHOST_CTL1_JKState0                                 0x0008
#define bmHOST_CTL1_USBReset0                                0x0010
#define bmHOST_CTL1_JKState1                                 0x0020
#define bmHOST_CTL1_USBReset1                                0x0040
#define bmHOST_CTL1_UD0                                      0x0080
#define bmHOST_CTL1_UD1                                      0x0100
#define bmHOST_CTL1_HOST                                     0x0200
#define bmHOST_CTL1_LOA                                      0x0400
#define bmHOST_CTL1_LOB                                      0x0800
#define bmHOST_CTL1_D0m                                      0x1000
#define bmHOST_CTL1_D0p                                      0x2000
#define bmHOST_CTL1_D1m                                      0x4000
#define bmHOST_CTL1_D1p                                      0x8000


/* MODE FIELD VALUES */

//#define HOST_MODE                                            0x0200 /* Host mode */
//#define DEVICE_MODE                                          0x0000 /* Device mode */

/* p_SPEED SELECT FIELD VALUES */

#define LOW_SPEED                                            0xFFFF /* Low speed */
#define FULL_SPEED                                           0x0000 /* Full speed */

#define B_SPEED_LOW                                          0x0800
#define B_SPEED_FULL                                         0x0000
#define A_SPEED_LOW                                          0x0400
#define A_SPEED_FULL                                         0x0000

/* FORCEn FIELD VALUES */

#define FORCE_K                                              0x0078 /* Force K state on associated port */
#define FORCE_SE0                                            0x0050 /* Force SE0 state on associated port */
#define FORCE_J                                              0x0028 /* Force J state on associated port */
#define FORCE_NORMAL                                         0x0000 /* Don't force associated port */

#define A_FORCE_K                                            0x0018 /* Force K state on A port */
#define A_FORCE_SE0                                          0x0010 /* Force SE0 state on associated port */
#define A_FORCE_J                                            0x0008 /* Force J state on associated port */
#define A_FORCE_NORMAL                                       0x0000 /* Don't force associated port */

#define B_FORCE_K                                            0x0060 /* Force K state on associated port */
#define B_FORCE_SE0                                          0x0040 /* Force SE0 state on associated port */
#define B_FORCE_J                                            0x0020 /* Force J state on associated port */
#define B_FORCE_NORMAL                                       0x0000 /* Don't force associated port */


/*********************************************************/
/*********************************************************/
/* HOST REGISTERS                                        */
/*********************************************************/
/*********************************************************/

/*********************************************************/
/* HOST n INTERRUPT ENABLE REGISTER [R/W]                */
/*********************************************************/

#define HOST1_IRQ_EN_REG                                     0xC08C /* Host 1 Interrupt Enable Register [R/W] */
#define SIE1_INT_EN_REG                                      0xC08C

#define HOST2_IRQ_EN_REG                                     0xC0AC /* Host 2 Interrupt Enable Register [R/W] */
#define SIE2_INT_EN_REG                                      0xC0AC

/* FIELDS */

#define VBUS_IRQ_EN                                          0x8000 /* VBUS Interrupt Enable (Available on HOST1 only)  */
#define ID_IRQ_EN                                            0x4000 /* ID Interrupt Enable (Available on HOST1 only) */
#define SOF_EOP_IRQ_EN                                       0x0200 /* SOF/EOP Interrupt Enable  */
#define B_WAKE_IRQ_EN                                        0x0080 /* Port B Wake Interrupt Enable  */