67300.h

此压缩包为杰得开发得z228的BSP的源代码,可以实现很多功能,尤其是视频解码有很好的效果.

/*                                                       */
/* HPI_DATA_PORT                                         */
/* HPI_ADDR_PORT                                         */
/* HPI_MBX_PORT                                          */
/* HPI_STAT_PORT                                         */
/*                                                       */
/*********************************************************/

/*********************************************************/
/*********************************************************/
/* CPU REGISTERS                                         */
/*********************************************************/
/*********************************************************/

/*********************************************************/
/* CPU FLAGS REGISTER [R]                                */
/*********************************************************/
#define CPU_FLAGS_REG                                        0xC000 /* CPU Flags Register [R] */
#define flags                                                0xC000

/* FIELDS */

#define GLOBAL_IRQ_EN                                        0x0010 /* Global Interrupt Enable */
#define NEG_FLG                                              0x0008 /* Negative Sign Flag */
#define OVF_FLG                                              0x0004 /* Overflow Flag */
#define CARRY_FLG                                            0x0002 /* Carry/Borrow Flag */
#define ZER0_FLG                                             0x0001 /* Zero Flag */

/*********************************************************/
/* BANK REGISTER [R/W]                                   */
/*********************************************************/

#define BANK_REG                                             0xC002 /* Bank Register [R/W] */
#define regbuf                                               0xC002 /* alias for BIOS code */

#define BANK                                                 0xFFE0 /* Bank */

/*********************************************************/
/* HARDWARE REVISION REGISTER [R]                        */
/*********************************************************/
/* First Silicon Revision is 0x0101. Revision number     */
/* will be incremented by one for each revision change.  */
/*********************************************************/

#define HW_REV_REG                                           0xC004 /* Hardware Revision Register [R] */

/*********************************************************/
/* INTERRUPT ENABLE REGISTER [R/W]                       */
/*********************************************************/

#define IRQ_EN_REG                                           0xC00E /* Interrupt Enable Register [R/W] */
#define intenb                                               0xC00E /* Alias for BIOS code */
#define INT_EN_REG                                           0xC00E /* BIOS Interrupt Enable Register Alias */

/* FIELDS */

#define OTG_IRQ_EN                                           0x1000 /* OTG Interrupt Enable */
#define SPI_IRQ_EN                                           0x0800 /* SPI Interrupt Enable */
#define HOST2_IRQ_EN                                         0x0200 /* Host 2 Interrupt Enable */
#define DEV2_IRQ_EN                                          0x0200 /* Device 2 Interrupt Enable */
#define HOST1_IRQ_EN                                         0x0100 /* Host 1 Interrupt Enable */
#define DEV1_IRQ_EN                                          0x0100 /* Device 1 Interrupt Enable */
#define HSS_IRQ_EN                                           0x0080 /* HSS Interrupt Enable */
#define IN_MBX_IRQ_EN                                        0x0040 /* In Mailbox Interrupt Enable */
#define OUT_MBX_IRQ_EN                                       0x0020 /* Out Mailbox Interrupt Enable */
#define DMA_IRQ_EN                                           0x0010 /* DMA Interrupt Enable */
#define UART_IRQ_EN                                          0x0008 /* UART Interrupt Enable */
#define GPIO_IRQ_EN                                          0x0004 /* GPIO Interrupt Enable */
#define TMR1_IRQ_EN                                          0x0002 /* Timer 1 Interrupt Enable */
#define TMR0_IRQ_EN                                          0x0001 /* Timer 0 Interrupt Enable */

/*  Alias bit mask definition for register IRQ_EN_REG */
#define bmINT_EN_TM0                                         0x0001
#define bmINT_EN_TM1                                         0x0002
#define bmINT_EN_GPIO                                        0x0004
#define bmINT_EN_UART                                        0x0008
#define bmINT_EN_DMA                                         0x0010
#define bmINT_EN_MBX_OUT                                     0x0020
#define bmINT_EN_MBX_IN                                      0x0040
#define bmINT_EN_HSP                                         0x0080
#define bmINT_EN_SIE1                                        0x0100
#define bmINT_EN_SIE2                                        0x0200
#define bmINT_EN_SPI                                         0x0800
#define bmINT_EN_OTG                                         0x1000

/* another define from sys_memmap */
#define GIO_IntCtl_MSK                                       0x0000
#define GIO_IntCtl_IRQ0En_BIT                                0x0000
#define GIO_IntCtl_IRQ0En_BM                                 0x0001
#define GIO_IntCtl_IRQ0Pol_BIT                               0x0001
#define GIO_IntCtl_IRQ0Pol_BM                                0x0002
#define GIO_IntCtl_IRQ1En_BIT                                0x0002
#define GIO_IntCtl_IRQ1En_BM                                 0x0004
#define GIO_IntCtl_IRQ1Pol_BIT                               0x0003
#define GIO_IntCtl_IRQ1Pol_BM                                0x0008
#define GIO_IntCtl_SX_BIT                                    0x0004
#define GIO_IntCtl_SX_BM                                     0x0010
#define GIO_IntCtl_SG_BIT                                    0x0005
#define GIO_IntCtl_SG_BM                                     0x0020
#define GIO_IntCtl_HX_BIT                                    0x0006
#define GIO_IntCtl_HX_BM                                     0x0040
#define GIO_IntCtl_HG_BIT                                    0x0007
#define GIO_IntCtl_HG_BM                                     0x0080

#define GIO_IntCtl_Mode_POS                                  0x0008
#define GIO_IntCtl_Mode_SIZ                                  0x0003
#define GIO_IntCtl_Mode_GPIO                                 0x0000
#define GIO_IntCtl_Mode_GPIObm                               0x0000
#define GIO_IntCtl_Mode_Flash                                0x0001
#define GIO_IntCtl_Mode_Flashbm                              0x0100
#define GIO_IntCtl_Mode_EPP                                  0x0002
#define GIO_IntCtl_Mode_EPPbm                                0x0200
#define GIO_IntCtl_Mode_SLV                                  0x0003
#define GIO_IntCtl_Mode_SLVbm                                0x0300
#define GIO_IntCtl_Mode_IDE                                  0x0004
#define GIO_IntCtl_Mode_IDEbm                                0x0400
#define GIO_IntCtl_Mode_HPI                                  0x0005
#define GIO_IntCtl_Mode_HPIbm                                0x0500
#define GIO_IntCtl_Mode_SCAN                                 0x0006
#define GIO_IntCtl_Mode_SCANbm                               0x0600
#define GIO_IntCtl_Mode_MDiag                                0x0007
#define GIO_IntCtl_Mode_MDiagbm                              0x0700

#define GIO_IntCtl_Bond_POS                                  0x000B
#define GIO_IntCtl_Bond_SIZ                                  0x0002
#define GIO_IntCtl_Bond_Embed                                0x0000
#define GIO_IntCtl_Bond_Embedbm                              0x0000
#define GIO_IntCtl_Bond_Flash                                0x0001
#define GIO_IntCtl_Bond_Flashbm                              0x0800
#define GIO_IntCtl_Bond_Mobile                               0x0002
#define GIO_IntCtl_Bond_Mobilebm                             0x1000

#define GIO_IntCtl_MD_BIT                                    0x000F

#define INT_Enable_T0_BIT                                    0x0000
#define INT_Enable_T0_BM                                     0x0001
#define INT_Enable_T1_BIT                                    0x0001
#define INT_Enable_T1_BM                                     0x0002
#define INT_Enable_GP_BIT                                    0x0002
#define INT_Enable_GP_BM                                     0x0004
#define INT_Enable_UART_BIT                                  0x0003
#define INT_Enable_UART_BM                                   0x0008
#define INT_Enable_FDMA_BIT                                  0x0004
#define INT_Enable_FDMA_BM                                   0x0010
#define INT_Enable_MBX_BIT                                   0x0006
#define INT_Enable_MBX_BM                                    0x0040
#define INT_Enable_HSS_BIT                                   0x0007
#define INT_Enable_HSS_BM                                    0x0080
#define INT_Enable_SIE1_BIT                                  0x0008
#define INT_Enable_SIE1_BM                                   0x0100
#define INT_Enable_SIE2_BIT                                  0x0009
#define INT_Enable_SIE2_BM                                   0x0200
#define INT_Enable_SPI_BIT                                   0x000B
#define INT_Enable_SPI_BM                                    0x0800

/*********************************************************/
/* CPU SPEED REGISTER [R/W]                              */
/*********************************************************/

#define CPU_SPEED_REG                                        0xC008 /* CPU Speed Register [R/W] */
#define P_SPEED                                              0xC008 /* Alias for BIOS code */

/* CPU SPEED REGISTER FIELDS 
**
** The Speed field in the CPU Speed Register provides a mechanism to
** divide the external clock signal down to operate the CPU at a lower 
** clock speed (presumedly for lower-power operation). The value loaded 
** into this field is a divisor and is calculated as (n+1). For instance, 
** if 3 is loaded into the field, the resulting CPU speed will be PCLK/4.
*/

#define CPU_SPEED                                            0x000F /* CPU Speed */

/*********************************************************/
/* POWER CONTROL REGISTER [R/W]                          */
/*********************************************************/

#define POWER_CTL_REG                                        0xC00A /* Power Control Register [R/W] */

/* FIELDS */

#define HOST2_WAKE_EN                                        0x4000 /* Host 2 Wake Enable */
#define DEV2_WAKE_EN                                         0x4000 /* Device 2 Wake Enable */
#define HOST1_WAKE_EN                                        0x1000 /* Host 1 Wake Enable */
#define DEV1_WAKE_EN                                         0x1000 /* Device 1 Wake Enable */
#define OTG_WAKE_EN                                          0x0800 /* OTG Wake Enable  */
#define HSS_WAKE_EN                                          0x0200 /* HSS Wake Enable  */
#define SPI_WAKE_EN                                          0x0100 /* SPI Wake Enable  */
#define HPI_WAKE_EN                                          0x0080 /* HPI Wake Enable  */
#define GPIO_WAKE_EN                                         0x0010 /* GPIO Wake Enable  */
#define SLEEP_EN                                             0x0002 /* Sleep Enable */
#define HALT_EN                                              0x0001 /* Halt Enable */

/*********************************************************/
/* BREAKPOINT REGISTER [R/W]                             */
/*********************************************************/

#define BKPT_REG                                             0xC014 /* Breakpoint Register [R/W] */

/*********************************************************/
/* USB DIAGNOSTIC REGISTER [W]                           */
/*********************************************************/

#define USB_DIAG_REG                                         0xC03C /* USB Diagnostic Register [R/W] */

/* FIELDS */

#define c2B_DIAG_EN                                          0x8000 /* Port 2B Diagnostic Enable */
#define c2A_DIAG_EN                                          0x4000 /* Port 2A Diagnostic Enable */
#define c1B_DIAG_EN                                          0x2000 /* Port 1B Diagnostic Enable */
#define c1A_DIAG_EN                                          0x1000 /* Port 1A Diagnostic Enable */
#define PULLDOWN_EN                                          0x0040 /* Pull-down resistors enable */
#define LS_PULLUP_EN                                         0x0020 /* Low-speed pull-up resistor enable */
#define FS_PULLUP_EN                                         0x0010 /* Full-speed pull-up resistor enable */
#define FORCE_SEL                                            0x0007 /* Control D+/- lines */

/* FORCE FIELD VALUES */

#define ASSERT_SE0                                           0x0004 /* Assert SE0 on selected ports */
#define TOGGLE_JK                                            0x0002 /* Toggle JK state on selected ports */