📄 z228_usb_msc.h
字号:
/*++* The content of this file or document is CONFIDENTIAL and PROPRIETARY* to Jade Technologies Co., Ltd. It is subject to the terms of a* License Agreement between Licensee and Jade Technologies Co., Ltd.* restricting among other things, the use, reproduction, distribution* and transfer. Each of the embodiments, including this information * and any derivative work shall retain this copyright notice.* * Copyright (c) 2006 Jade Technologies Co., Ltd. * All rights reserved.Module Name: z228_usb_msc.HAbstract: OTG USB Function (Mass Storage) Platform-Dependent Driver header.--*/#ifndef _Z228USBMSC_H_#define _Z228USBMSC_H_#include <windows.h>#include <usbfntypes.h>#include <usbfn.h>#define Z228_REG_FORCE_FULL_SPEED_VAL _T("ForceFullSpeed")// Memory Mapped Window Numbers#define WINDOW_CONFIG_NUM 0#define WINDOW_8051_NUM 1#define WINDOW_FIFO_NUM 2// Can be used for Interrupt and Interrupt Enable Reg - common bit def#define EP0_INT_INTR 0x1#define EP1_INT_INTR 0x2#define EP2_INT_INTR 0x4#define EP3_INT_INTR 0x8#define EP4_INT_INTR 0x10#define RegOpenKey(hkey, lpsz, phk) \ RegOpenKeyEx((hkey), (lpsz), 0, 0, (phk))#ifndef SHIP_BUILD#define STR_MODULE _T("Z228")#define SETFNAME() LPCTSTR pszFname = STR_MODULE _T(__FUNCTION__) _T(":")#else#define SETFNAME()#endif/**************************************************************************************** * USB device/endpoint management registers */#define UDC_BASE 0#define UHC_BASE 0#define PHY_UDC_BASE PHYS_USB_BASE //#define PHY_UHC_BASE Z228_UHC_BASE/* UDC Registers Memory Map layout */#define UDC_FIFO_SIZE 0x4000#define UDC_TX_FIFO_ADR UDC_BASE#define UDC_RX_FIFO_ADR (UDC_BASE + 0x40000)#define UDC_TLI_ADR (UDC_BASE + 0x44000)#define UDC_MAC_ADR (UDC_BASE + 0x44400)#define UDC_DIU_ADR (UDC_BASE + 0x45000)#define UDC_TLI_REG(x) (UDC_TLI_ADR + (x))#define UDC_MAC_REG(x) (UDC_MAC_ADR + (x))#define UDC_DIU_REG(x) (UDC_DIU_ADR + (x))/* FIFOs */#define UDC_TX_FIFO(n) (UDC_TX_FIFO_ADR + UDC_FIFO_SIZE * (n))#define UDC_RX_FIFO (UDC_RX_FIFO_ADR)/* UDC TLI registers */#define UDC_TX_CONTROL(n) UDC_TLI_REG(0x10*(n))#define UDC_TX_SENDSTALL (1 << 0)#define UDC_TX_SENDNAK (1 << 1)#define UDC_TX_FLUSHFIFO (1 << 2)#define UDC_TX_FIFOREADY (1 << 3)#define UDC_TX_STATUS(n) UDC_TLI_REG(0x004 + 0x10 * (n))#define UDC_TX_GOOD_STATUS (1 << 0)#define UDC_TX_DATASENT (1 << 1)#define UDC_TX_BELOWTHR (1 << 2)#define UDC_TX_NAKSENT (1 << 3)#define UDC_TX_UNDERRUN (1 << 4)#define UDC_TX_ISOTXDONE (1 << 5)#define UDC_TX_FIFOSIZE(n) UDC_TLI_REG(0x008 + 0x10 * (n))#define UDC_TX_TRANSFER_SIZE(n) UDC_TLI_REG(0x00c + 0x10 * (n))#define UDC_RX_CONTROL(n) UDC_TLI_REG(0x100 + 0x10 * (n))#define UDC_RX_SENDSTALL (1 << 0) #define UDC_RX_SENDNAK (1 << 1) #define UDC_RX_FLUSHFIFO (1 << 2) #define UDC_RX_FIFOREADY (1 << 3) #define UDC_SENDSTALL (1 << 0) #define UDC_SENDNAK (1 << 1) #define UDC_FLUSHFIFO (1 << 2) #define UDC_FIFOREADY (1 << 3) #define UDC_CONFIG UDC_TLI_REG(0x200)#define UDC_CONFIG_SPEEDLOW (1 << 1) #define UDC_CONFIG_SPEEDFULL 0x0003#define UDC_CONFIG_REMOTEWAKE (1 << 2) #define UDC_CONFIG_SELFPOWERED (1 << 3) #define UDC_CONFIG_SYNCFRAME (1 << 4) #define UDC_CSR_PRG_SUP (1 << 5) #define UDC_CSR_DONE (1 << 6)#define UDC_SET_DESC_SUP (1 << 7)#define UDC_DEVICE_MODE (1 << 8)#define UDC_SCALE_DOWN (1 << 9) #define UDC_SOFT_DISCONNECT (1 << 10)#define UDC_STATUS_0 (1 << 11) #define UDC_STATUS_1 (1 << 12)#define UDC_STATUS UDC_TLI_REG(0x204)#define UDC_STATUS_TS_SHIFT 21#define UDC_STATUS_TS_MASK 0x7ff#define UDC_STATUS_SUSP (1 << 12) #define UDC_STATUS_ALT_SHIFT 8#define UDC_STATUS_ALT_MASK 0xf#define UDC_STATUS_INTF_SHIFT 4#define UDC_STATUS_INTF_MASK 0xf#define UDC_STATUS_CFG_SHIFT 0#define UDC_STATUS_CFG_MASK 0xf#define UDC_INTR UDC_TLI_REG(0x208)#define UDC_SETCFG_INTR (1 << 0)#define UDC_SETINTF_INTR (1 << 1)#define UDC_BUSRESET_INTR (1 << 3)#define UDC_SUSPEND_INTR (1 << 4)#define UDC_SOF_INTR (1 << 5)#define UDC_SETUP_REV_INTR (1 << 6)#define UDC_OUT_REV_INTR (1 << 7)#define UDC_PORT_STATUS_INTR (1 << 8)#define UDC_OTG_STATUS_INTR (1 << 9)#define UDC_I2C_INTR (1 << 10)//#define UN_SETUP_INTR (UDC_BUSRESET_INTR|UDC_SUSPEND_INTR|UDC_OUT_REV_INTR|UDC_PORT_STATUS_INTR|UDC_OTG_STATUS_INTR|UDC_I2C_INTR)#define UN_SETUP_INTR (UDC_BUSRESET_INTR|UDC_SUSPEND_INTR|UDC_PORT_STATUS_INTR|UDC_OTG_STATUS_INTR|UDC_I2C_INTR)#define UN_BUS_INTR (UDC_BUSRESET_INTR | UDC_SUSPEND_INTR |UDC_OTG_STATUS_INTR)#define UDC_INTR_MASK (UDC_SETCFG_INTR | UDC_SETUP_REV_INTR | UDC_OUT_REV_INTR|UDC_SETINTF_INTR)#define UDC_INTR_ENABLE UDC_TLI_REG(0x20c)#define UDC_RX_FIFOSIZE UDC_TLI_REG(0x210) #define UDC_ENDP_INTR_ENABLE UDC_TLI_REG(0x214)#define enable_out_ep_intr(n) (UDC_ENDP_INTR_ENABLE |= 1 << (n + 15))#define disable_out_ep_intr(n) (UDC_ENDP_INTR_ENABLE &= ~(1 << (n + 15)))#define enable_in_ep_intr(n) (UDC_ENDP_INTR_ENABLE |= 1 << (n - 1))#define disable_in_ep_intr(n) (UDC_ENDP_INTR_ENABLE &= ~(1 << (n - 1)))#define UDC_THRESHOLD UDC_TLI_REG(0x218)#define UDC_TX_THRESH_SHIFT 0#define UDC_TX_THRESH_MASK 0x3ff #define UDC_RX_THRESH_SHIFT 16#define UDC_RX_THRESH_MASK 0x3ff #define UDC_RX_STATUS UDC_TLI_REG(0x21c)#define UDC_RX_GOOD_STATUS (1 << 0)#define UDC_RX_STATUS_COMPLETE (1 << 1)#define UDC_RX_THRESH_ABOVE (1 << 2)#define UDC_RX_OVERRUN (1 << 4)#define UDC_RX_ENDP_SHIFT 16#define UDC_RX_ENDP_MASK 0xf#define UDC_RX_SIZE_SHIFT 22#define UDC_RX_SIZE_MASK 0x3ff #define UDC_SETUP_STATUS UDC_TLI_REG(0x220)#define UDC_SETUP_GOOD_STATUS (1 << 0)#define UDC_SETUP_STATUS_COMPLETE (1 << 1)#define UDC_SETUP_AFTER_OUT (1 << 15)#define UDC_SETUP_ENDP_SHIFT 16#define UDC_SETUP_ENDP_MASK 0x000f#define UDC_ENDP_INTR UDC_TLI_REG(0x224)#define UDC_FRAMENUM UDC_TLI_REG(0x228)#define UDC_SETUP_DATA_LOW UDC_TLI_REG(0x300)#define UDC_SETUP_DATA_HIGH UDC_TLI_REG(0x304)#define UDC_SLAVE_BIU_DELAY_COUNT UDC_TLI_REG(0x308)#define UDC_I2C UDC_TLI_REG(0x30c)#define UDC_PORT_STATUS (UDC_BASE + 0x44c54)#define UDC_OTG_CSR (UDC_BASE + 0x44c94)/* FS OTG-MAC registers (USB Device Mode) */#define UDC_ENDP_INFO(n) UDC_MAC_REG( 0x04*(n+1) )#define UDC_ENDP_NUM_SHIFT 0#define UDC_ENDP_NUM_MASK 0xF#define UDC_ENDP_DIR 0x10#define UDC_ENDP_TYPE_SHIFT 5#define UDC_ENDP_TYPE_MASK 0x3#define UDC_ENDP_CFG_NUM_SHIFT 7#define UDC_ENDP_CFG_NUM_MASK 0xF#define UDC_ENDP_INTF_NUM_SHIFT 11#define UDC_ENDP_INTF_NUM_MASK 0xF#define UDC_ENDP_ALT_SET_SHIFT 15#define UDC_ENDP_ALT_SET_MASK 0xF#define UDC_ENDP_MAX_PACKET_SHIFT 19#define UDC_ENDP_MAX_PACKET_MASK 0x3FF#define EP_OUT (0 << 4)#define EP_IN (1 << 4)#define EP_CONTROL (0 << UDC_ENDP_TYPE_SHIFT)#define EP_ISO (1 << UDC_ENDP_TYPE_SHIFT)#define EP_BULK (2 << UDC_ENDP_TYPE_SHIFT)#define EP_INTERRUPT (3 << UDC_ENDP_TYPE_SHIFT)/* FS OTG-DIU registers (USB Device Mode) */#define UDC_DIU_TX_DMA(n) UDC_DIU_REG( 0x04*(n) )#define UDC_DIU_RX_DMA(n) UDC_DIU_REG( 0x040 + 0x04*(n))#define UDC_DIU_TSSHIFT 16#define UDC_DIU_TSMASK 0x0000ffff#define UDC_DIU_TFFSHIFT 15#define UDC_DIU_TFFMASK 0x00000001#define UDC_DIU_DSESHIFT 14#define UDC_DIU_DSEMASK 0x00000001#define UDC_DIU_TTSHIFT 12#define UDC_DIU_TTMASK 0x00000003#define UDC_DIU_RSTSHIFT 11#define UDC_DIU_RSTMASK 0x00000001#define UDC_DIU_REQSHIFT 6#define UDC_DIU_REQMASK 0x0000001f#define UDC_DIU_BSSHIFT 2#define UDC_DIU_BSMASK 0x0000000f#define UDC_DIU_DESCSHIFT 1#define UDC_DIU_DESCMASK 0x00000001#define UDC_DIU_EPACT 0x00000001#define UDC_DIU_TT_CTRL 0#define UDC_DIU_TT_ISOC 1#define UDC_DIU_TT_BULK 2#define UDC_DIU_TT_INTR 3#define UDC_DIU_BS_4 0x2#define UDC_DIU_BS_16 0x4#define UDC_DIU_BS_32 0x5#define UDC_DIU_BS_64 0x6#define UDC_DIU_BS_128 0x7#define UDC_DIU_BS_256 0x8#define UDC_DIU_BS_512 0x9#define UDC_DIU_BS_1024 0xA/* Register for USB Host Controller */#define UHC_TLI_BASE (UHC_BASE + 0x44800)#define UHC_CSR_ADR (UHC_BASE + 0x44800)#define UHC_MAC_ADR (UHC_BASE + 0x44c00)#define UHC_DIU_ADR (UHC_BASE + 0x45000)#define UHC_CSR_REG(x) (UHC_CSR_ADR + (x))#define UHC_MAC_REG(x) (UHC_MAC_ADR + (x))#define UHC_DIU_REG(x) (UHC_DIU_ADR + (x))#define UHC_INTR_ENABLE (UHC_TLI_BASE + 0x04)#define UHC_CONTROL (UHC_TLI_BASE + 0x0c)#define UHC_FLUSHFIFO 0x001#define UHC_FIFOSIZE (UHC_TLI_BASE + 0x10)#define UHC_FRAME_INTVL UHC_MAC_REG(0x34) #define UHC_ROOT_HUB_PORT_0 UHC_MAC_REG(0x54)#define RH_PS_PPS 0x00000100 /* port power status */#define UHC_OTG_CSR UHC_MAC_REG(0x94)#define UHC_SRP_STATUS_OK 0x00000001#define UHC_SRP_STATUS_CHANGE 0x00000002#define UHC_HNP_STATUS_OK 0x00000004#define UHC_HNP_STATUS_CHANGE 0x00000008#define UHC_SRP_DETECT 0x00000010#define UHC_SRP_DETECT_CHANGE 0x00000020#define UHC_HNP_DETECT 0x00000040#define UHC_HNP_DETECT_CHANGE 0x00000080#define UHC_CONN_ID 0x00000100#define UHC_CONN_ID_CHANGE 0x00000200#define UHC_MODE_DEVICE 0x00000400#define UHC_SRP_START 0x00010000#define UHC_HNP_START 0x00020000#define UHC_HNP_ENABLE_HOST 0x00040000#define UHC_HNP_ENABLE_DEVICE 0x00080000#define UHC_SRP_CAPABLE 0x00100000#define UHC_HNP_CAPABLE 0x00200000#define UHC_INTR UHC_CSR_REG(0x00)#define UHC_STATUS_INTR 0x0001#define UHC_RX_THRESH_INTR 0x0002#define UHC_TX_THRESH_INTR 0x0004#define UHC_SOF_INTR 0x0008#define UHC_PORT_STATUS_INTR 0x0100#define UHC_OTG_STATUS_INTR 0x0200#define UHC_I2C_STATUS_INTR 0x0400#define UHC_THRESHOLD UHC_CSR_REG(0x14)//********************************************************************************************#define OTG_MODE_DEVICE 0x00000400#define DEV_MODE 1#define HOST_MODE 0#define UHC_INTR_MASK 0x70f/* Register for Z228 System Controller */#define Z228_SC_BASE 0x20020000#define Z228_RESET (Z228_SC_BASE + 0x110)#define Z228_RESET_nUSBRES (1 << 8)#define Z228_RESET_nUSB48RES (1 << 9)#define Z228_RESET_nUSBPLLRES (1 << 10)#define Z228_RESET_nUSB12RES (1 << 11)#define Z228_CLOCK (Z228_SC_BASE + 0x114)#define Z228_CLOCK_USB133 (1 << 19)#define Z228_CLOCK_USB48 (1 << 20)//********************************************************************************************//******************************************************************************************** /* Max packet size */#define EP0_PACKETSIZE 64 #define EP0_MAXPACKETSIZE 64#define UDC_MAX_ENDPOINTS 7 #define IN_EP_MASK 0x7#define OUT_EP_MASK (IN_EP_MASK << 16)#define ENDP_INTR_MASK (IN_EP_MASK | OUT_EP_MASK)#define UDC_TX_THRESHOLD 32 #define UDC_RX_THRESHOLD 32 #define UDC_PHY_FIFO_SIZE 64//********************************************************************************************#endif // _Z228USBMSC_H_⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -