pl031.h

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/*   The content of this file or document is CONFIDENTIAL and PROPRIETARY
*   to Jade Technologies Co., Ltd.  It is subjected to the terms of a
*   License Agreement between Licensee and Jade Technologies Co., Ltd.
*   restricting among other things, the use, reproduction, distribution
*   and transfer.  Each of the embodiments, including this information 
*   and any derivative work shall retain this copyright notice.
* 
*   Copyright (c) 2004 - 2005 Jade Technologies Co., Ltd. 
*   All rights reserved.
*/
// ----------------------------------------------------------------
// File:     pl031.h,v
// Revision: 1.0
// ----------------------------------------------------------------
// $ 
//

// pl031.h - Real Time Clock

#ifndef pl031_h
#define pl031_h


// Structure containing the mapping of the RTC registers

typedef volatile struct _rtcif_tag 
{
    const DWORD DR;         /* Data register    */
          DWORD MR;         /* Match register   */
          DWORD LR;         /* Load register    */
          DWORD CR;         /* Control register */
          DWORD IMSC;       /* Interupt mask set and clear register */
    const DWORD RIS;        /* Raw interrupt status regisdter       */
    const DWORD MIS;        /* Masked interrupt status register     */
          DWORD ICR;        /* Interrupt clear register             */
    const DWORD padding0[1008]; 
    const DWORD PeriphID0;  /* Peripheral ID register0 bits [7:0]   */
    const DWORD PeriphID1;  /* Peripheral ID register0 bits [15:8]  */
    const DWORD PeriphID2;  /* Peripheral ID register0 bits [23:16] */
    const DWORD PeriphID3;  /* Peripheral ID register0 bits [31:24] */
    const DWORD PCellID0;   /* PrimeCell ID register bits [7:0]     */
    const DWORD PCellID1;   /* PrimeCell ID register bits [15:8]    */
    const DWORD PCellID2;   /* PrimeCell ID register bits [23:16]   */
    const DWORD PCellID3;   /* PrimeCell ID register bits [31:24]   */

} vstRTCRegs, *pvstRTCRegs;

#endif // pl031_h