📄 fw_arm.s
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;
; The content of this file or document is CONFIDENTIAL and PROPRIETARY
; to Jade Technologies Co., Ltd. It is subjected to the terms of a
; License Agreement between Licensee and Jade Technologies Co., Ltd.
; restricting among other things, the use, reproduction, distribution
; and transfer. Each of the embodiments, including this information
; and any derivative work shall retain this copyright notice.
;
; Copyright (c) 2004 - 2005 Jade Technologies Co., Ltd.
; All rights reserved.
; ----------------------------------------------------------------
; File: fw_arm.s,v
; Revision: 1.0
; ----------------------------------------------------------------
; $
;
;
; Module Name:
;
; fw_arm.s
;
; Abstract:
;
; This module implements the code necessary to initialize the HW and
; Kernel interface routines.
;
;
; This one source file is used to provide Startup code both for the
; Ethernet Boot Loader, and for the WinCE kernel. The default is to
; build for the WinCE kernel
;
IF :LNOT: :DEF: EBOOT
GBLL EBOOT
EBOOT SETL {FALSE}
ENDIF
IF :LNOT: :DEF: EXEFLASH
GBLL EXEFLASH
EXEFLASH SETL {FALSE}
ENDIF
OPT 2 ; disable listing in fw_arm.lst
INCLUDE kxarm.h
INCLUDE armmacros.inc
INCLUDE sizes.inc
INCLUDE bits.inc
INCLUDE platform.inc
INCLUDE cpumodes.inc
INCLUDE target.inc
INCLUDE sp810.inc
;eddie add
INCLUDE mpmcinit.inc
OPT 1 ; enable listing in fw_arm.lst
IMPORT ARMInitSerial
IMPORT ARMPutHex
IMPORT ARMWriteString
IF EBOOT
IMPORT EbootMain
ELSE
IMPORT KernelStart
ENDIF
IF EBOOT :LOR: :LNOT:EXEFLASH
IMPORT EverythingRelocate
ENDIF
IF :DEF: EXAMPLE_MEMCONFIG
IMPORT ARMConfigMemory
ENDIF
CP15ControlInit EQU 0xc0001078 ; Async. Bus mode
; I-Cache enabled
; Little-Endian
; MMU Disabled
STARTUPTEXT
LEAF_ENTRY StartUp
; There are two ways into StartUp: from the bootmonitor/reset or from
; wake up. In either case, the processor should be in a privileged mode
; (e.g. SVC) with the MMU disabled. If the MMU might be active, there
; needs to be code to ensure that the executable is still at the next
; address when the MMU is turned off.
;
; disable all interrupts, set SVC mode
mov r0, #(SVC32Mode :OR: NoINTS)
msr cpsr_c, r0
IF EBOOT
;****************************************************************
;* Judge running address
;****************************************************************
; Must update our return address
adr r1, remap_addr
cmp r1, #EBOOT_RAMBASE
bgt RAM_boot
ldr r0, =Z228_FLASH_BASE
add pc, r0, r1
RAM_boot
;^^^^^^^^^^^^^^^^^^^^^^
ldr r5, =0x20030024
mov r6, #0x01
str r6, [r5]
;^^^^^^^^^^^^^^^^^^^^^^
;Judge if remap has been done ?
remap_addr
ldr r0, =PHYS_SC_BASE ; r0 -> System Controller
ldr r1, [r0, #ARM_MAPMOVE]
cmp r1, #1
beq INIT
;remap
mov r1, #2
str r1, [r0, #ARM_BOOTMAPCLR] ;REMAPSTATIC=0
mov r1, #1
str r1, [r0, #ARM_MAPMOVE] ;remaped to SDRAM
; Switch to 266MHz Normal Mode
;Switch to SCLK
ldr r1, =Z228_CLKSEL
mov r0, #0x1
str r0, [r1]
;Switch PLL0 to 266MHz
ldr r2, =Z228_PLL0
ldr r0, =Z228_266M
str r0, [r2]
; Wait > 500 us
mov r0, #512
w1 sub r0, r0, #1
cmp r0,#1
bne w1
; Switch back from SCLK
ldr r1, =Z228_CLKSEL
mov r0, #0x0
str r0, [r1]
;^^^^^^^^^^^^^^^^^^^^^^
ldr r1, =0x20030024
mov r0, #0x11
str r0, [r1]
;^^^^^^^^^^^^^^^^^^^^^^
;sdram init
bl mpmcinit
;^^^^^^^^^^^^^^^^^^^^^^
ldr r1, =0x20030024
mov r0, #0xff
str r0, [r1]
;^^^^^^^^^^^^^^^^^^^^^^
ENDIF
;**************************************
;
; Here is a good place to do any speed (CPU, memory etc) setup
; We do not do any here as the boot monitor is used to do this for now
;
;zq we use 32k ref_clk
; Set all the timers to 1MHz
INIT
ldr r0, =PHYS_SC_BASE
ldr r1, [r0, #ARM_SCCtrl]
orr r1, r1, #(SCCtrlTimer0EnSel :OR: SCCtrlTimer1EnSel :OR: SCCtrlTimer2EnSel :OR: SCCtrlTimer3EnSel)
str r1, [r0, #ARM_SCCtrl]
ContinueSetup
; Only used temporarily, but setup a stack for use by 'C' routines;
; Use only the first 32KB of the area. Remember this is a full descending
; based stack.
ldr sp, =TEMP_STACK_BASE
IF :DEF: EXAMPLE_MEMCONFIG
BL ARMConfigMemory
ENDIF
; Now reset all CP15 features
ldr r0, =CP15ControlInit
WRMMU_STATE r0
mov r0, #0x0
WRMMU_FlushTB r0 ; flush TLBs
WRCACHE_FlushIDC r0 ; flush caches
; Example code to support remapping to flash after a reset
IF :DEF: EXAMPLE_FLASHREMAP
; Make sure we're running from the physical memory address and
; not an address mapped to 0 (the normal reset state).
GOTO_ROM r0, r1
ENDIF
DISABLE_INTS r0, r1 ; Ints -> IRQ; LEDs
IF EBOOT :LOR: :LNOT:EXEFLASH
;
; Relocate code from Flash to RAM if necessary. This step is required
; for EBOOT as it's code runs from physical, not virtual, addresses. It
; is optional for Win CE, though running from RAM increases performance
;
; Returns with r0 = linked address for Startup, -1 if currently
; executing in the correct place
;
; NOTE: Since the eboot/nk image is built to execute from RAM but we're
; currently executing out of flash, make sure this call is a relative
; branch. Once the code is relocated to RAM, absolute address references
; are fine.
;
; The branch with link instruction will do a relative branch and since we
; don't care about Thumb/ARM mode switching, it works fine here.
;
bl EverythingRelocate
; branch to final execution address if necessary
cmp r0, #-1
addne r0, r0, #(RealStartup - StartUp)
movne pc, r0
ENDIF
RealStartup
; init the debug serial port and say "hello".
bl ARMInitSerial
;add by shzhang
; Wait > 100 ms
mov r0, #128000
w100 sub r0, r0, #1
cmp r0,#1
bne w100
adr r0, HelloMsg
bl ARMWriteString
adr r0, StackMsg
bl ARMWriteString
mov r0, sp
bl ARMPutHex
adr r0, EndMsg
bl ARMWriteString
IF EBOOT
CALL EbootMain
ELSE
; (r0) = physical address of OEMMemoryMap
adr r0, OEMAddressTable
bl KernelStart
ENDIF
; control should never return to this routine; if it does, output
; some debug & spin
adr r0, ByeMsg
bl ARMWriteString
spin b spin
IF EBOOT
HelloMsg DCB 13, 10, "Z228 Ethernet Boot Loader", 13, 10, 0
ByeMsg DCB 13, 10, "ARMVPB_Eboot returned!", 13, 10, 0
ELSE
HelloMsg DCB 13, 10, "WindowsCE on Z228", 13, 10, 0
ByeMsg DCB 13, 10, "KernelStart returned!", 13, 10, 0
ENDIF
StackMsg DCB " Stack Pointer: ", 0
EndMsg DCB 13, 10, 0
ENTRY_END StartUp
ALIGN 4
IF :LNOT: EBOOT
INCLUDE mapx20t.inc
ENDIF
;****************************************************************
mpmcinit PROC
mov r6, lr
ldr r1, =Z228_MPMCDyReadConfig
mov r0, #0x0
str r0, [r1]
; Z228_MPMCDytRP = 0x2
;-------------------------------
ldr r1, =Z228_MPMCDytRP
mov r0, #0x2
str r0, [r1]
; Z228_MPMCDytRAS = 0x5
;-------------------------------
ldr r1, =Z228_MPMCDytRAS
mov r0, #0x5
str r0, [r1]
; Z228_MPMCDytSREX = 0x9
;-------------------------------
ldr r1, =Z228_MPMCDytSREX
mov r0, #0x9
str r0, [r1]
; Z228_MPMCDytWR = 0x2
;-------------------------------
ldr r1, =Z228_MPMCDytWR
mov r0, #0x2
str r0, [r1]
; Z228_MPMCDytRC = 0x8
;-------------------------------
ldr r1, =Z228_MPMCDytRC
mov r0, #0x8
str r0, [r1]
; Z228_MPMCDytRFC = 0x9
;-------------------------------
ldr r1, =Z228_MPMCDytRFC
mov r0, #0x9
str r0, [r1]
; Z228_MPMCDytXSR = 0x9
;-------------------------------
ldr r1, =Z228_MPMCDytXSR
str r0, [r1]
; Z228_MPMCDytRRD = 0x2
;-------------------------------
ldr r1, =Z228_MPMCDytRRD
mov r0, #0x2
str r0, [r1]
; Z228_MPMCDytMRD = 0x2
;-------------------------------
ldr r1, =Z228_MPMCDytRRD
str r0, [r1]
; Z228_MPMCDytCDLR = 0x1
;-------------------------------
ldr r1, =Z228_MPMCDytCDLR
mov r0, #0x1
str r0, [r1]
; Z228_MPMCDyRasCas0 = 0x203
;-------------------------------
ldr r1, =Z228_MPMCDyRasCas0
ldr r0, =Z228_MPMCDyRasCas_Value
str r0, [r1]
; Z228_MPMCDyRasCas1 = 0x203
;-------------------------------
ldr r1, =Z228_MPMCDyRasCas1
str r0, [r1]
; Z228_MPMCDyConfig0 = 0x4680
;-------------------------------
ldr r1, =Z228_MPMCDyConfig0
ldr r0, =Z228_MPMCDyConfig_Value
str r0, [r1]
; Z228_MPMCDyConfig1 = 0x4680
;-------------------------------
ldr r1, =Z228_MPMCDyConfig1
str r0, [r1]
; Z228_MPMCDyControl = 0x183
;-------------------------------
ldr r1, =Z228_MPMCDyControl
ldr r0, =Z228_MPMCDyControl_Value1
str r0, [r1]
; Delay
;-------------------------------
mov r2, #0x30
w2 sub r2, r2, #1
cmp r2, #1
bne w2
; Z228_MPMCDyControl = 0x103
;-------------------------------
ldr r1, =Z228_MPMCDyControl
ldr r0, =Z228_MPMCDyControl_Value2
str r0, [r1]
; Z228_MPMCDyRefresh = 0x1
;-------------------------------
ldr r1, =Z228_MPMCDyRefresh
mov r0, #0x1
str r0, [r1]
; Delay
;-------------------------------
mov r2, #0x30
w3 sub r2, r2, #1
cmp r2,#1
bne w3
; Z228_MPMCDyRefresh = 0x1c/0x75 266mhz
;-------------------------------
ldr r1, =Z228_MPMCDyRefresh
mov r0, #0x75
str r0, [r1]
; Z228_MPMCDyControl = 0x83
;-------------------------------
ldr r1, =Z228_MPMCDyControl
ldr r0, =Z228_MPMCDyControl_Value3
str r0, [r1]
; Read Memory
;-------------------------------
ldr r4, =Z228_SDRAM_READ1
ldr r3, [r4]
ldr r4, =Z228_SDRAM_READ2
ldr r3, [r4]
; Z228_MPMCDyControl = 0x3
;-------------------------------
ldr r1, =Z228_MPMCDyControl
mov r0, #0x3
str r0, [r1]
IF :DEF: CONFIG_Z228_MPMCTIMEOUT
ldr r1, =Z228_MPMCAHBTimeOut0
mov r0, #2
str r0, [r1]
ldr r1, =Z228_MPMCAHBTimeOut5
mov r0, #0x80
str r0, [r1]
ldr r1, =Z228_MPMCAHBTimeOut7
mov r0, #0x80
str r0, [r1]
ENDIF
; Mpmc Dynamic Memory Config complete
; -----------------------------------------------------------------------------
mov pc, r6
ENDP
END
; EOF fw_arm.s
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