📄 cachemode.s
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;
; The content of this file or document is CONFIDENTIAL and PROPRIETARY
; to Jade Technologies Co., Ltd. It is subjected to the terms of a
; License Agreement between Licensee and Jade Technologies Co., Ltd.
; restricting among other things, the use, reproduction, distribution
; and transfer. Each of the embodiments, including this information
; and any derivative work shall retain this copyright notice.
;
; Copyright (c) 2004 - 2005 Jade Technologies Co., Ltd.
; All rights reserved.
; ----------------------------------------------------------------
; File: cachemode.s,v
; Revision: 1.0
; ----------------------------------------------------------------
; $
OPT 2 ; disable listing
INCLUDE kxarm.h
OPT 1 ; reenable listing
OPT 128 ; disable listing of macro expansions
INCLUDE armmacros.inc
TEXTAREA
LEAF_ENTRY OEMARMCacheMode
;++
; Routine Description:
; Sets the C and B bits to be used to build page tables
;
; C and B bits are part of the page table entries and control write through
; vs. write back cache modes, cacheability, and write buffer use.
;
; *** Note: The C and B bit functionality is processor specific. Consult the
; CPU hardware manual for the CPU in question before altering these bit
; configurations. ***
;
; This default configuration (C=B=1)works on all current ARM CPU's and gives
; the following behaviour
; ARM92x: write back cache mode
;
; The four valid options are:
; ARM_NoBits 0x00000000
; ARM_CBit 0x00000008
; ARM_BBit 0x00000004
; ARM_CBBits 0x0000000C
;
; Syntax:
; DWORD OEMARMCacheMode(void);
;
; Arguments:
; -- none --
;
; Return Value:
; r0 must contain the desired C and B bit configuration. See description above
; for valid bit patterns.
;
; Caution:
; The value placed in r0 MUST be an immediate data value and NOT a predefined
; constant. This function is called at a point in the boot cycle where the
; memory containing predefined constants has NOT been initialized yet.
; --
mov r0, #0x0C ; Default is writeback cached. Earlier versions of Windows CE
; gave better performance with writethrough and no explicit
; cache flushing; now that the frequency of cache flushing is
; much lower, writeback is better.
RETURN
END
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