📄 phy.h
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/* Standard MII Registers */
#define MII_CTRL_REG 0x00 /* MII Control Register : r/w */
#define MII_STAT_REG 0x01 /* MII Status Register: ro */
#define MII_PHY_ID0_REG 0x02 /* MII PHY ID register: r/w */
#define MII_PHY_ID1_REG 0x03 /* MII PHY ID register: r/w */
#define MII_ANA_REG 0x04 /* MII Auto-Neg Advertisement: r/w */
#define MII_ANP_REG 0x05 /* MII Auto-Neg Link Partner: ro */
#define MII_AN_EXP_REG 0x06 /* MII Auto-Neg Expansion: ro */
#define MII_GB_CTRL_REG 0x09 /* MII 1000Base-T control register */
#define MII_GB_STAT_REG 0x0a /* MII 1000Base-T Status register */
#define MII_ESR_REG 0x0f /* MII Extended Status register */
/* Non-standard MII Registers */
#define MII_ECR_REG 0x10 /* MII Extended Control Register */
#define MII_AUX_REG 0x18 /* MII Auxiliary Control/Status Register */
#define MII_ASSR_REG 0x19 /* MII Auxiliary Status Summary Reg */
#define MII_EXTN_STAT_REG 0x1b /* MII extended phy specific status regoster*/
#define MII_GSR_REG 0x1c /* MII General status (BROADCOM) */
#define MII_MSSEED_REG 0x1d /* MII Master/slave seed (BROADCOM) */
#define MII_TEST2_REG 0x1f /* MII Test reg (BROADCOM) */
/* MII Control Register: bit definitions */
#define MII_CTRL_SS_MSB (1 << 6) /* Speed select, MSb */
#define MII_CTRL_CST (1 << 7) /* Collision Signal test */
#define MII_CTRL_FD (1 << 8) /* Full Duplex */
#define MII_CTRL_RAN (1 << 9) /* Restart Autonegotiation */
#define MII_CTRL_IP (1 << 10) /* Isolate Phy */
#define MII_CTRL_PD (1 << 11) /* Power Down */
#define MII_CTRL_AE (1 << 12) /* Autonegotiation enable */
#define MII_CTRL_SS_LSB (1 << 13) /* Speed select, LSb */
#define MII_CTRL_LE (1 << 14) /* Loopback enable */
#define MII_CTRL_RESET (1 << 15) /* PHY reset */
#define MII_CTRL_SS(_x) ((_x) & (MII_CTRL_SS_LSB|MII_CTRL_SS_MSB))
#define MII_CTRL_SS_10 0
#define MII_CTRL_SS_100 (MII_CTRL_SS_LSB)
#define MII_CTRL_SS_1000 (MII_CTRL_SS_MSB)
#define MII_CTRL_SS_INVALID (MII_CTRL_SS_LSB | MII_CTRL_SS_MSB)
#define MII_CTRL_SS_MASK (MII_CTRL_SS_LSB | MII_CTRL_SS_MSB)
/*
* MII Status Register: See 802.3, 1998 pg 544
*/
#define MII_STAT_EXT (1 << 0) /* Extended Registers */
#define MII_STAT_JBBR (1 << 1) /* Jabber Detected */
#define MII_STAT_LA (1 << 2) /* Link Active */
#define MII_STAT_AN_CAP (1 << 3) /* Autoneg capable */
#define MII_STAT_RF (1 << 4) /* Remote Fault */
#define MII_STAT_AN_DONE (1 << 5) /* Autoneg complete */
#define MII_STAT_MF_PS (1 << 6) /* Preamble suppression */
#define MII_STAT_ES (1 << 8) /* Extended status (R15) */
#define MII_STAT_HD_100_T2 (1 << 9) /* Half duplex 100Mb/s supported */
#define MII_STAT_FD_100_T2 (1 << 10)/* Full duplex 100Mb/s supported */
#define MII_STAT_HD_10 (1 << 11)/* Half duplex 100Mb/s supported */
#define MII_STAT_FD_10 (1 << 12)/* Full duplex 100Mb/s supported */
#define MII_STAT_HD_100 (1 << 13)/* Half duplex 100Mb/s supported */
#define MII_STAT_FD_100 (1 << 14)/* Full duplex 100Mb/s supported */
#define MII_STAT_100_T4 (1 << 15)/* Full duplex 100Mb/s supported */
/*
* MII Link Advertisment
*/
#define MII_ANA_ASF (1 << 0)/* Advertise Selector Field */
#define MII_ANA_HD_10 (1 << 5)/* Half duplex 10Mb/s supported */
#define MII_ANA_FD_10 (1 << 6)/* Full duplex 10Mb/s supported */
#define MII_ANA_HD_100 (1 << 7)/* Half duplex 100Mb/s supported */
#define MII_ANA_FD_100 (1 << 8)/* Full duplex 100Mb/s supported */
#define MII_ANA_T4 (1 << 9)/* T4 */
#define MII_ANA_PAUSE (1 << 10)/* Pause supported */
#define MII_ANA_ASYM_PAUSE (1 << 11)/* Asymmetric pause supported */
#define MII_ANA_RF (1 << 13)/* Remote fault */
#define MII_ANA_NP (1 << 15)/* Next Page */
#define MII_ANA_ASF_802_3 (1) /* 802.3 PHY */
/*
* 1000Base-T Control Register
*/
#define MII_GB_CTRL_MS_MAN (1 << 12) /* Manual Master/Slave mode */
#define MII_GB_CTRL_MS (1 << 11) /* Master/Slave negotiation mode */
#define MII_GB_CTRL_PT (1 << 10) /* Port type */
#define MII_GB_CTRL_ADV_1000FD (1 << 9) /* Advertise 1000Base-T FD */
#define MII_GB_CTRL_ADV_1000HD (1 << 8) /* Advertise 1000Base-T HD */
/*
* 1000Base-T Status Register
*/
#define MII_GB_STAT_MS_FAULT (1 << 15) /* Master/Slave Fault */
#define MII_GB_STAT_MS (1 << 14) /* Master/Slave, 1 == Master */
#define MII_GB_STAT_LRS (1 << 13) /* Local receiver status */
#define MII_GB_STAT_RRS (1 << 12) /* Remote receiver status */
#define MII_GB_STAT_LP_1000FD (1 << 11) /* Link partner 1000FD capable */
#define MII_GB_STAT_LP_1000HD (1 << 10) /* Link partner 1000HD capable */
#define MII_GB_STAT_IDE (0xff << 0) /* Idle error count */
/*
* IEEE Extended Status Register
*/
#define MII_ESR_1000_X_FD (1 << 15) /* 1000Base-T FD capable */
#define MII_ESR_1000_X_HD (1 << 14) /* 1000Base-T HD capable */
#define MII_ESR_1000_T_FD (1 << 13) /* 1000Base-T FD capable */
#define MII_ESR_1000_T_HD (1 << 12) /* 1000Base-T FD capable */
/*
* MII Extended Control Register (BROADCOM)
*/
#define MII_ECR_FE (1 << 0) /* FIFO Elasticity */
#define MII_ECR_TLLM (1 << 1) /* Three link LED mode */
#define MII_ECR_ET_IPG (1 << 2) /* Extended XMIT IPG mode */
#define MII_ECR_FLED_OFF (1 << 3) /* Force LED off */
#define MII_ECR_FLED_ON (1 << 4) /* Force LED on */
#define MII_ECR_ELT (1 << 5) /* Enable LED traffic */
#define MII_ECR_RS (1 << 6) /* Reset Scrambler */
#define MII_ECR_BRSA (1 << 7) /* Bypass Receive Sym. align */
#define MII_ECR_BMLT3 (1 << 8) /* Bypass MLT3 Encoder/Decoder */
#define MII_ECR_BSD (1 << 9) /* Bypass Scramble/Descramble */
#define MII_ECR_B4B5B (1 << 10) /* Bypass 4B/5B Encode/Decode */
#define MII_ECR_FI (1 << 11) /* Force Interrupt */
#define MII_ECR_ID (1 << 12) /* Interrupt Disable */
#define MII_ECR_TD (1 << 13) /* XMIT Disable */
#define MII_ECR_DAMC (1 << 14) /* DIsable Auto-MDI Crossover */
#define MII_ECR_10B (1 << 15) /* 1 == 10B, 0 == GMII */
/*
* GSR (BROADCOM)
*/
#define MII_GSR_FD (1 << 0) /* Full duplex active */
#define MII_GSR_SI (1 << 1) /* Speed 0-->10, 1 --> 100 */
#define MII_GSR_FORCE (1 << 2) /* Force 0-->10, 1--> 100 */
#define MII_GSR_AN (1 << 3) /* Autonegotiation enabled */
/*
* Auxiliary Control/Status Register
*/
#define MII_AUX_LD (1<<14) /* Link Integrity test disabled in PHY */
/*
* Auxiliary Status Summary Register (ASSR - Broadcom BCM5400)
*/
#define MII_ASSR_PRTD (1 << 0) /* Pause resolution/XMIT direction */
#define MII_ASSR_PRRD (1 << 1) /* Pause resolution/RCV direction */
#define MII_ASSR_LS (1 << 2) /* Link Status (1 == link up) */
#define MII_ASSR_LPNPA (1 << 3) /* Link partner next page cap */
#define MII_ASSR_LPANA (1 << 4) /* Link Partner AN capable */
#define MII_ASSR_ANPR (1 << 5) /* Autoneg page received */
#define MII_ASSR_RF (1 << 6) /* Remote Fault */
#define MII_ASSR_PDF (1 << 7) /* Parallel detection fault */
#define MII_ASSR_HCD (7 << 8) /* Current operating speed */
#define MII_ASSR_ANNPW (1 << 11) /* Auto-neg next page wait */
#define MII_ASSR_ANABD (1 << 12) /* Auto-neg Ability detected */
#define MII_ASSR_ANAD (1 << 13) /* Auto-neg ACK detect */
#define MII_ASSR_ANCA (1 << 14) /* Auto-neg complete ACK */
#define MII_ASSR_ANC (1 << 15) /* AUto-neg complete */
#define MII_ASSR_HCD_FD_1000 (7 << 8)
#define MII_ASSR_HCD_HD_1000 (6 << 8)
#define MII_ASSR_HCD_FD_100 (5 << 8)
#define MII_ASSR_HCD_T4_100 (4 << 8)
#define MII_ASSR_HCD_HD_100 (3 << 8)
#define MII_ASSR_HCD_FD_10 (2 << 8)
#define MII_ASSR_HCD_HD_10 (1 << 8)
#define MII_ASSR_HCD_NC (0 << 8) /* Not complete */
#define MII_TEST2_MS_SEL (1 << 11)
#define MII_MSSEED_SEED 0x3ff
#define PHY_MIN_REG 0
#define PHY_MAX_REG 0x1f
#define PHY_ADDR_MIN 0
#define PHY_ADDR_MAX 31
#define PHY_NUM_PORTS (PHY_ADDR_MAX - PHY_ADDR_MIN + 1)
/* Clause 45 MIIM */
#define PHY_C45_DEV_RESERVED 0x00
#define PHY_C45_DEV_PMA_PMD 0x01
#define PHY_C45_DEV_WIS 0x02
#define PHY_C45_DEV_PCS 0x03
#define PHY_C45_DEV_PHYXS 0x04
#define PHY_C45_DEV_DTEXS 0x05
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