clk.txt

时钟发生器 clkgen 利用外来时钟信号clk 来生成一系列时钟信号clk1、fetch、alu_clk 送往CPU的其他部件

时钟发生器
时钟发生器 clkgen 利用外来时钟信号clk 来生成一系列时钟信号clk1、fetch、alu_clk 送往CPU的其他部件。其中fetch是外来时钟 clk 的八分频信号。利用fetch的上升沿来触发CPU控制器开始执行一条指令，同时fetch信号还将控制地址多路器输出指令地址和数据地址。clk1信号用作指令寄存器、累加器、状态控制器的时钟信号。alu_clk 则用于触发算术逻辑运算单元。
module clk_gen (clk,reset,clk1,clk2,clk4,fetch,alu_clk);
input clk,reset;
output clk1,clk2,clk4,fetch,alu_clk;
wire clk,reset;
reg clk2,clk4,fetch,alu_clk;
reg[7:0] state;
parameter   S1 = 8'b00000001,
        S2 = 8'b00000010,
        S3 = 8'b00000100,
        S4 = 8'b00001000,
        S5 = 8'b00010000,
        S6 = 8'b00100000,
        S7 = 8'b01000000,
        S8 = 8'b10000000,
      idle = 8'b00000000;

assign clk1 = ~clk;

always @(negedge clk)
  if(reset)
      begin
          clk2 <= 0;
          clk4 <= 1;
          fetch <= 0;
          alu_clk <= 0;
          state <= idle;
      end
  else
      begin
        case(state)
          S1:
              begin
                  clk2 <= ~clk2;
                alu_clk <= ~alu_clk;           
                  state <= S2;
              end
          S2:
              begin
                clk2 <= ~clk2;
                clk4 <= ~clk4;
              alu_clk <= ~alu_clk;
                state <= S3;
              end
          S3:
              begin   
                clk2 <= ~clk2;
                state <= S4;
              end
          S4:
              begin
                clk2 <= ~clk2;
                clk4 <= ~clk4;
                fetch <= ~fetch;
                state <= S5;
              end
          S5:
              begin
                clk2 <= ~clk2;
                state <= S6;
              end
          S6:
              begin
                  clk2 <= ~clk2;
                  clk4 <= ~clk4;
                  state <= S7;
                end
          S7:
                begin
                  clk2 <= ~clk2;
                  state <= S8;
                end
          S8:
                begin
                  clk2 <= ~clk2;
                  clk4 <= ~clk4;
                  fetch <= ~fetch;
                  state <= S1;
                end
          idle:     state <= S1;   
          default:   state <= idle;           
        endcase
  end
endmodule
//--------------------------------------------------------------------------------

由于在时钟发生器的设计中采用了同步状态机的设计方法，不但使clk_gen模块的源程序可以被各种综合器综合，也使得由其生成的clk1、clk2、clk4、fetch、alu_clk 在跳变时间同步性能上有明显的提高，为整个系统的性能提高打下了良好的基础。