start167.a66

this application program demonstrate programming and simulation of the on-chip CAN (controller area

; R_CLKCFG: Clock Generation Mode (XTAL PLL factor; RSTCON.13 .. RSTCON.15)
R_CLKCFG   EQU     0       ; 0 = CPU CLOCK = XTAL * 2.5
;                          ; 1 = CPU CLOCK = XTAL / 2.0
;                          ; 2 = CPU CLOCK = XTAL * 1.5
;                          ; 3 = CPU CLOCK = XTAL (direct drive)
;                          ; 4 = CPU CLOCK = XTAL * 5.0
;                          ; 5 = CPU CLOCK = XTAL * 2.0
;                          ; 6 = CPU CLOCK = XTAL * 3.0
;                          ; 7 = CPU CLOCK = XTAL * 4.0
;
;------------------------------------------------------------------------------
;
; BUSCON1/ADDRSEL1 .. BUSCON4/ADDRSEL4 Initialization
; ===================================================
;
;
; BUSCON1/ADDRSEL1
; --- Set BUSCON1 = 1 to initialize the BUSCON1/ADDRSEL1 registers
$SET (BUSCON1 = 0) ; Uv2/Dave
;
; Define the start address and the address range of Chip Select 1 (CS1#) 
; This values are used to set the ADDRSEL1 register
%DEFINE(ADDRESS1) (00000H) ; Uv2/Dave
%DEFINE(RANGE1) (4K) ; Uv2/Dave
;  
; MCTC1: Memory Cycle Time (BUSCON1.0 .. BUSCON1.3):
; Note: if RDYEN1 == 1 a maximum number of 7 waitstates can be selected
_MCTC1 EQU 4 ; Uv2/Dave
;
; RWDC1: Read/Write Signal Delay (BUSCON1.4):
_RWDC1 EQU 0 ; Uv2/Dave
;                       ; 1 = No Delay Time  0   States
;
; MTTC1: Memory Tri-state Time (BUSCON1.5):
_MTTC1 EQU 0 ; Uv2/Dave
;                       ; 1 = No Delay Time  0   States
;
; BTYP1: External Bus Configuration Control (BUSCON1.6 .. BUSCON1.7):
_BTYP1 EQU 0 ; Uv2/Dave
;                       ; 1 = 8 Bit Multiplexed
;                       ; 2 = 16 Bit Non Multiplexed
;                       ; 3 = 16 Bit Multiplexed
;
; ALECTL1: ALE Lengthening Control Bit (BUSCON1.9):
_ALECTL1 EQU 0 ; Uv2/Dave
;
; BUSACT1: Bus Active Control Bit (BUSCON1.10):
_BUSACT1 EQU 0 ; Uv2/Dave
                        ; = 1 external (ADDRSEL1) bus enabled
;
; RDYEN1: READY# Input Enable control bit (BUSCON1.12):
_RDYEN1 EQU 0 ; Uv2/Dave
;                       ; 1 = READY# function enabled
;
; RDY_AS1: Synchronous / Asynchronous READY# Input (BUSCON1.3):
; Note: This bit is only valid if _RDYEN1 == 1.
_RDY_AS1 EQU    0       ; 0 = synchronous READY# input
;                       ; 1 = asynchronous READY# input
;
; CSREN1: Read Chip Select Enable bit (BUSCON1.14):
_CSREN1 EQU 0 ; Uv2/Dave
;                       ; 1 = CS1# is generated for the duration of read
;
; CSWEN1: Write Chip Select Enable bit (BUSCON1.15):
_CSWEN1 EQU 0 ; Uv2/Dave
;                       ; 1 = CS1# is generated for the duration of write
;
;
; BUSCON2/ADDRSEL2
; --- Set BUSCON2 = 1 to initialize the BUSCON2/ADDRSEL2 registers
$SET (BUSCON2 = 0) ; Uv2/Dave
;
; Define the start address and the address range of Chip Select 2 (CS2#) 
; This values are used to set the ADDRSEL2 register
%DEFINE(ADDRESS2) (00000H) ; Uv2/Dave
%DEFINE(RANGE2) (4K) ; Uv2/Dave
;  
; MCTC2: Memory Cycle Time (BUSCON2.0 .. BUSCON2.3):
; Note: if RDYEN2 == 1 a maximum number of 7 waitstates can be selected
_MCTC2 EQU 15 ; Uv2/Dave
;
; RWDC2: Read/Write Signal Delay (BUSCON2.4):
_RWDC2 EQU 0 ; Uv2/Dave
;                       ; 1 = No Delay Time  0   States
;
; MTTC2: Memory Tri-state Time (BUSCON2.5):
_MTTC2 EQU 0 ; Uv2/Dave
;                       ; 1 = No Delay Time  0   States
;
; BTYP2: External Bus Configuration Control (BUSCON2.6 .. BUSCON2.7):
_BTYP2 EQU 0 ; Uv2/Dave
;                       ; 1 = 8 Bit Multiplexed
;                       ; 2 = 16 Bit Non Multiplexed
;                       ; 3 = 16 Bit Multiplexed
;
; ALECTL2: ALE Lengthening Control Bit (BUSCON2.9):
_ALECTL2 EQU 0 ; Uv2/Dave
;
; BUSACT2: Bus Active Control Bit (BUSCON2.10):
_BUSACT2 EQU 0 ; Uv2/Dave
                        ; = 1 external (ADDRSEL2) bus enabled
;
; RDYEN2: READY# Input Enable control bit (BUSCON2.12):
_RDYEN2 EQU 0 ; Uv2/Dave
;                       ; 1 = READY# function enabled
;
; RDY_AS2: Synchronous / Asynchronous READY# Input (BUSCON2.3):
; Note: This bit is only valid if _RDYEN2 == 1.
_RDY_AS2 EQU    0       ; 0 = synchronous READY# input
;                       ; 1 = asynchronous READY# input
;
; CSREN2: Read Chip Select Enable bit (BUSCON2.14):
_CSREN2 EQU 0 ; Uv2/Dave
;                       ; 1 = CS2# is generated for the duration of read
;
; CSWEN2: Write Chip Select Enable bit (BUSCON2.15):
_CSWEN2 EQU 0 ; Uv2/Dave
;                       ; 1 = CS2# is generated for the duration of write
;
;
; BUSCON3/ADDRSEL3
; --- Set BUSCON3 = 1 to initialize the BUSCON3/ADDRSEL3 registers
$SET (BUSCON3 = 0) ; Uv2/Dave
;
; Define the start address and the address range of Chip Select 3 (CS3#) 
; This values are used to set the ADDRSEL3 register
%DEFINE(ADDRESS3) (00000H) ; Uv2/Dave
%DEFINE(RANGE3) (4K) ; Uv2/Dave
;  
; MCTC3: Memory Cycle Time (BUSCON3.0 .. BUSCON3.3):
; Note: if RDYEN3 == 1 a maximum number of 7 waitstates can be selected
_MCTC3 EQU 15 ; Uv2/Dave
;
; RWDC3: Read/Write Signal Delay (BUSCON3.4):
_RWDC3 EQU 0 ; Uv2/Dave
;                       ; 1 = No Delay Time  0   States
;
; MTTC3: Memory Tri-state Time (BUSCON3.5):
_MTTC3 EQU 0 ; Uv2/Dave
;                       ; 1 = No Delay Time  0   States
;
; BTYP3: External Bus Configuration Control (BUSCON3.6 .. BUSCON3.7):
_BTYP3 EQU 0 ; Uv2/Dave
;                       ; 1 = 8 Bit Multiplexed
;                       ; 2 = 16 Bit Non Multiplexed
;                       ; 3 = 16 Bit Multiplexed
;
; ALECTL3: ALE Lengthening Control Bit (BUSCON3.9):
_ALECTL3 EQU 0 ; Uv2/Dave
;
; BUSACT3: Bus Active Control Bit (BUSCON3.10):
_BUSACT3 EQU 0 ; Uv2/Dave
                        ; = 1 external (ADDRSEL3) bus enabled
;
; RDYEN3: READY# Input Enable control bit (BUSCON3.12):
_RDYEN3 EQU 0 ; Uv2/Dave
;                       ; 1 = READY# function enabled
;
; RDY_AS3: Synchronous / Asynchronous READY# Input (BUSCON3.3):
; Note: This bit is only valid if _RDYEN3 == 1.
_RDY_AS3 EQU    0       ; 0 = synchronous READY# input
;                       ; 1 = asynchronous READY# input
;
; CSREN3: Read Chip Select Enable bit (BUSCON3.14):
_CSREN3 EQU 0 ; Uv2/Dave
;                       ; 1 = CS3# is generated for the duration of read
;
; CSWEN3: Write Chip Select Enable bit (BUSCON3.15):
_CSWEN3 EQU 0 ; Uv2/Dave
;                       ; 1 = CS3# is generated for the duration of write
;
;
; BUSCON4/ADDRSEL4
; --- Set BUSCON4 = 1 to initialize the BUSCON4/ADDRSEL4 registers
$SET (BUSCON4 = 0) ; Uv2/Dave
;
; Define the start address and the address range of Chip Select 4 (CS4#) 
; This values are used to set the ADDRSEL4 register
%DEFINE(ADDRESS4) (00000H) ; Uv2/Dave
%DEFINE(RANGE4) (4K) ; Uv2/Dave
;  
; MCTC4: Memory Cycle Time (BUSCON4.0 .. BUSCON4.3):
; Note: if RDYEN4 == 1 a maximum number of 7 waitstates can be selected
_MCTC4 EQU 15 ; Uv2/Dave
;
; RWDC4: Read/Write Signal Delay (BUSCON4.4):
_RWDC4 EQU 0 ; Uv2/Dave
;                       ; 1 = No Delay Time  0   States
;
; MTTC4: Memory Tri-state Time (BUSCON4.5):
_MTTC4 EQU 0 ; Uv2/Dave
;                       ; 1 = No Delay Time  0   States
;
; BTYP4: External Bus Configuration Control (BUSCON4.6 .. BUSCON4.7):
_BTYP4 EQU 0 ; Uv2/Dave
;                       ; 1 = 8 Bit Multiplexed
;                       ; 2 = 16 Bit Non Multiplexed
;                       ; 3 = 16 Bit Multiplexed
;
; ALECTL4: ALE Lengthening Control Bit (BUSCON4.9):
_ALECTL4 EQU 0 ; Uv2/Dave
;
; BUSACT4: Bus Active Control Bit (BUSCON4.10):
_BUSACT4 EQU 0 ; Uv2/Dave
                        ; = 1 external (ADDRSEL4) bus enabled
;
; RDYEN4: READY# Input Enable control bit (BUSCON4.12):
_RDYEN4 EQU 0 ; Uv2/Dave
;                       ; 1 = READY# function enabled
;
; RDY_AS4: Synchronous / Asynchronous READY# Input (BUSCON4.3):
; Note: This bit is only valid if _RDYEN4 == 1.
_RDY_AS4 EQU    0       ; 0 = synchronous READY# input
;                       ; 1 = asynchronous READY# input
;
; CSREN4: Read Chip Select Enable bit (BUSCON4.14):
_CSREN4 EQU 0 ; Uv2/Dave
;                       ; 1 = CS4# is generated for the duration of read
;
; CSWEN4: Write Chip Select Enable bit (BUSCON4.15):
_CSWEN4 EQU 0 ; Uv2/Dave
;                       ; 1 = CS4# is generated for the duration of write
;
;------------------------------------------------------------------------------

$IF TINY
$SET (DPPUSE = 0)
$ENDIF

_STKSZ SET 0 ; Uv2/Dave
_STKSZ1         SET     0               ; size is 512 Words
$IF (STK_SIZE = 0)
_STKSZ1         SET     1               ; size is 256 Words
$ENDIF
$IF (STK_SIZE = 1)
_STKSZ          SET     1
_STKSZ1         SET     2               ; size is 128 Words
$ENDIF
$IF (STK_SIZE = 2)
_STKSZ          SET     2
_STKSZ1         SET     3               ; size is  64 Words
$ENDIF
$IF (STK_SIZE = 3)
_STKSZ          SET     3
_STKSZ1         SET     4               ; size is  32 Words
$ENDIF
$IF (STK_SIZE = 4)
_STKSZ          SET     4
$ENDIF
$IF (STK_SIZE = 5)
_STKSZ          SET     5
$ENDIF
$IF (STK_SIZE = 6)
_STKSZ          SET     6
$ENDIF
$IF (STK_SIZE = 7)
_STKSZ          SET     7
$ENDIF


$IF NOT TINY
ASSUME  DPP3:SYSTEM
ASSUME  DPP2:NDATA
$ENDIF

NAME    ?C_STARTUP
PUBLIC  ?C_STARTUP

$IF MEDIUM OR LARGE OR HLARGE
Model   LIT     'FAR'
$ELSE
Model   LIT     'NEAR'
$ENDIF

EXTRN   main:Model

PUBLIC          ?C_USRSTKBOT

?C_USERSTACK    SECTION DATA PUBLIC 'NDATA'
$IF NOT TINY
NDATA           DGROUP  ?C_USERSTACK
$ENDIF
?C_USRSTKBOT:
                DS      USTSZ           ; Size of User Stack
?C_USERSTKTOP:
?C_USERSTACK    ENDS

?C_MAINREGISTERS        REGDEF  R0 - R15

$IF (STK_SIZE = 7)

?C_SYSSTACK     SECTION DATA PUBLIC 'IDATA'
$IF NOT TINY
SDATA           DGROUP  ?C_SYSSTACK
$ENDIF
_BOS:                                   ; bottom of system stack
                DS      SSTSZ           ; Size of User Stack
_TOS:                                   ; top of system stack
?C_SYSSTACK     ENDS

$ELSE
; Setup Stack Overflow
_TOS    EQU     0FC00H                          ; top of system stack
_BOS    EQU     _TOS - (1024 >> _STKSZ1)        ; bottom of system stack
$ENDIF