plus32.v

来自「Nios 的用户定义接口逻辑实例」· Verilog 代码 · 共 39 行

// <interface to user logic> gesign entity;
// the module use  interface to user logic of nios;
// address  0 is clera counter value and clera irq signal(only write);
// address  1 is output clock count of high plus width (only write);    
// address  2 is create irq width (only write);
module plus32 ( clk, irq, chipselect, write , writedata , address, plus_signal);
       input       clk;
       input       chipselect;
       input       write;
       input[31:0] writedata;
       input[1:0]  address;
       output      plus_signal;
       output      irq;
       reg         load;
       always  @(posedge clk)
          if (chipselect && write && (address == 0))
             load  <= writedata[0];

       reg  [31:0] data_count;
       always  @(posedge clk)
          if (chipselect && write && (address == 2))
             data_count  <= writedata;

       reg  [31:0] data_latch;
       always  @(posedge clk)
          if (chipselect && write && (address == 1))
             data_latch  <= writedata;
             
       reg  [31:0] countl;
       always  @(posedge clk)
          if (load)
              countl  <= 0;
          else 
              countl  <= countl + 1;
              
       wire  irq          =   (countl >= data_count);      
       wire  plus_signal  =   (countl < data_latch);               
endmodule