📄 elec.tan.rpt
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Timing Analyzer report for ELEC
Fri Jun 15 17:03:56 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. tsu
6. tco
7. th
8. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+--------+--------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+--------+--------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 3.274 ns ; D ; Q~reg0 ; -- ; CLK ; 0 ;
; Worst-case tco ; N/A ; None ; 8.838 ns ; Q~reg0 ; Q ; CLK ; -- ; 0 ;
; Worst-case th ; N/A ; None ; -3.222 ns ; D ; Q~reg0 ; -- ; CLK ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+--------+--------+------------+----------+--------------+
+-------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+-----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+-----+-------------+
; Device Name ; EP1C3T144C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
; Clock Settings ; Clock ; ; CLK ; ;
+-------------------------------------------------------+--------------------+------+-----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK ; CLOCK ; User Pin ; 50.0 MHz ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+--------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+------+--------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+------+--------+----------+
; N/A ; None ; 3.274 ns ; D ; Q~reg0 ; CLK ;
+-------+--------------+------------+------+--------+----------+
+--------------------------------------------------------------+
; tco ;
+-------+--------------+------------+--------+----+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+--------+----+------------+
; N/A ; None ; 8.838 ns ; Q~reg0 ; Q ; CLK ;
+-------+--------------+------------+--------+----+------------+
+--------------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+------+--------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+------+--------+----------+
; N/A ; None ; -3.222 ns ; D ; Q~reg0 ; CLK ;
+---------------+-------------+-----------+------+--------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Fri Jun 15 17:03:56 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ELEC -c ELEC --timing_analysis_only
Info: No valid register-to-register data paths exist for clock "CLK"
Info: tsu for register "Q~reg0" (data pin = "D", clock pin = "CLK") is 3.274 ns
Info: + Longest pin to register delay is 7.822 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_11; Fanout = 1; PIN Node = 'D'
Info: 2: + IC(6.044 ns) + CELL(0.309 ns) = 7.822 ns; Loc. = LC_X12_Y8_N5; Fanout = 1; REG Node = 'Q~reg0'
Info: Total cell delay = 1.778 ns ( 22.73 % )
Info: Total interconnect delay = 6.044 ns ( 77.27 % )
Info: + Micro setup delay of destination is 0.037 ns
Info: - Shortest clock path from clock "CLK" to destination register is 4.585 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 1; CLK Node = 'CLK'
Info: 2: + IC(2.405 ns) + CELL(0.711 ns) = 4.585 ns; Loc. = LC_X12_Y8_N5; Fanout = 1; REG Node = 'Q~reg0'
Info: Total cell delay = 2.180 ns ( 47.55 % )
Info: Total interconnect delay = 2.405 ns ( 52.45 % )
Info: tco from clock "CLK" to destination pin "Q" through register "Q~reg0" is 8.838 ns
Info: + Longest clock path from clock "CLK" to source register is 4.585 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 1; CLK Node = 'CLK'
Info: 2: + IC(2.405 ns) + CELL(0.711 ns) = 4.585 ns; Loc. = LC_X12_Y8_N5; Fanout = 1; REG Node = 'Q~reg0'
Info: Total cell delay = 2.180 ns ( 47.55 % )
Info: Total interconnect delay = 2.405 ns ( 52.45 % )
Info: + Micro clock to output delay of source is 0.224 ns
Info: + Longest register to pin delay is 4.029 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y8_N5; Fanout = 1; REG Node = 'Q~reg0'
Info: 2: + IC(1.921 ns) + CELL(2.108 ns) = 4.029 ns; Loc. = PIN_53; Fanout = 0; PIN Node = 'Q'
Info: Total cell delay = 2.108 ns ( 52.32 % )
Info: Total interconnect delay = 1.921 ns ( 47.68 % )
Info: th for register "Q~reg0" (data pin = "D", clock pin = "CLK") is -3.222 ns
Info: + Longest clock path from clock "CLK" to destination register is 4.585 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 1; CLK Node = 'CLK'
Info: 2: + IC(2.405 ns) + CELL(0.711 ns) = 4.585 ns; Loc. = LC_X12_Y8_N5; Fanout = 1; REG Node = 'Q~reg0'
Info: Total cell delay = 2.180 ns ( 47.55 % )
Info: Total interconnect delay = 2.405 ns ( 52.45 % )
Info: + Micro hold delay of destination is 0.015 ns
Info: - Shortest pin to register delay is 7.822 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_11; Fanout = 1; PIN Node = 'D'
Info: 2: + IC(6.044 ns) + CELL(0.309 ns) = 7.822 ns; Loc. = LC_X12_Y8_N5; Fanout = 1; REG Node = 'Q~reg0'
Info: Total cell delay = 1.778 ns ( 22.73 % )
Info: Total interconnect delay = 6.044 ns ( 77.27 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Fri Jun 15 17:03:56 2007
Info: Elapsed time: 00:00:01
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