elec.tan.qmsg

密码锁程序`第一次上传的`希望大家多多下载多多指点

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jun 15 17:03:56 2007 " "Info: Processing started: Fri Jun 15 17:03:56 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off ELEC -c ELEC --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ELEC -c ELEC --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "CLK " "Info: No valid register-to-register data paths exist for clock \"CLK\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "Q~reg0 D CLK 3.274 ns register " "Info: tsu for register \"Q~reg0\" (data pin = \"D\", clock pin = \"CLK\") is 3.274 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.822 ns + Longest pin register " "Info: + Longest pin to register delay is 7.822 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns D 1 PIN PIN_11 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_11; Fanout = 1; PIN Node = 'D'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { D } "NODE_NAME" } } { "DCFQ.vhd" "" { Text "C:/Documents and Settings/user/桌面/ELEC/DCFQ.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.044 ns) + CELL(0.309 ns) 7.822 ns Q~reg0 2 REG LC_X12_Y8_N5 1 " "Info: 2: + IC(6.044 ns) + CELL(0.309 ns) = 7.822 ns; Loc. = LC_X12_Y8_N5; Fanout = 1; REG Node = 'Q~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.353 ns" { D Q~reg0 } "NODE_NAME" } } { "DCFQ.vhd" "" { Text "C:/Documents and Settings/user/桌面/ELEC/DCFQ.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.778 ns ( 22.73 % ) " "Info: Total cell delay = 1.778 ns ( 22.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.044 ns ( 77.27 % ) " "Info: Total interconnect delay = 6.044 ns ( 77.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.822 ns" { D Q~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.822 ns" { D D~out0 Q~reg0 } { 0.000ns 0.000ns 6.044ns } { 0.000ns 1.469ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "DCFQ.vhd" "" { Text "C:/Documents and Settings/user/桌面/ELEC/DCFQ.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 4.585 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 4.585 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_93 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "DCFQ.vhd" "" { Text "C:/Documents and Settings/user/桌面/ELEC/DCFQ.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.405 ns) + CELL(0.711 ns) 4.585 ns Q~reg0 2 REG LC_X12_Y8_N5 1 " "Info: 2: + IC(2.405 ns) + CELL(0.711 ns) = 4.585 ns; Loc. = LC_X12_Y8_N5; Fanout = 1; REG Node = 'Q~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.116 ns" { CLK Q~reg0 } "NODE_NAME" } } { "DCFQ.vhd" "" { Text "C:/Documents and Settings/user/桌面/ELEC/DCFQ.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 47.55 % ) " "Info: Total cell delay = 2.180 ns ( 47.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.405 ns ( 52.45 % ) " "Info: Total interconnect delay = 2.405 ns ( 52.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.585 ns" { CLK Q~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.585 ns" { CLK CLK~out0 Q~reg0 } { 0.000ns 0.000ns 2.405ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.822 ns" { D Q~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.822 ns" { D D~out0 Q~reg0 } { 0.000ns 0.000ns 6.044ns } { 0.000ns 1.469ns 0.309ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.585 ns" { CLK Q~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.585 ns" { CLK CLK~out0 Q~reg0 } { 0.000ns 0.000ns 2.405ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}