elec.fit.rpt

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; Internal Atom Count - Fit Attempt 1                                            ; 4          ;
; LE/ALM Count - Fit Attempt 1                                                   ; 4          ;
; LAB Count - Fit Attempt 1                                                      ; 2          ;
; Outputs per Lab - Fit Attempt 1                                                ; 0.500      ;
; Inputs per LAB - Fit Attempt 1                                                 ; 2.000      ;
; Global Inputs per LAB - Fit Attempt 1                                          ; 0.000      ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 0:1;2:1    ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:2        ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:1;3:1    ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:1;2:1    ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 0:1;3:1    ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:1;2:1    ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:1;1:1    ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:2        ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:1;2:1    ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:2        ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 0:1;1:1    ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:1;1:1    ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 0:1;1:1    ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:2        ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 0:2        ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:2        ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:2        ;
; LEs in Chains - Fit Attempt 1                                                  ; 0          ;
; LEs in Long Chains - Fit Attempt 1                                             ; 0          ;
; LABs with Chains - Fit Attempt 1                                               ; 0          ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0          ;
; Time - Fit Attempt 1                                                           ; 0          ;
+--------------------------------------------------------------------------------+------------+


+--------------------------------------------------+
; Advanced Data - Placement                        ;
+-------------------------------------+------------+
; Name                                ; Value      ;
+-------------------------------------+------------+
; Auto Fit Point 2 - Fit Attempt 1    ; ff         ;
; Early Wire Use - Fit Attempt 1      ; 0          ;
; Early Slack - Fit Attempt 1         ; 2147483639 ;
; Auto Fit Point 3 - Fit Attempt 1    ; ff         ;
; Auto Fit Point 4 - Fit Attempt 1    ; ff         ;
; Mid Wire Use - Fit Attempt 1        ; 0          ;
; Mid Slack - Fit Attempt 1           ; 2147483639 ;
; Late Wire Use - Fit Attempt 1       ; 0          ;
; Late Slack - Fit Attempt 1          ; 2147483639 ;
; Auto Fit Point 5 - Fit Attempt 1    ; ff         ;
; Time - Fit Attempt 1                ; 0          ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.016      ;
+-------------------------------------+------------+


+--------------------------------------------------+
; Advanced Data - Routing                          ;
+-------------------------------------+------------+
; Name                                ; Value      ;
+-------------------------------------+------------+
; Early Slack - Fit Attempt 1         ; 2147483639 ;
; Mid Slack - Fit Attempt 1           ; 2147483639 ;
; Late Slack - Fit Attempt 1          ; 2147483639 ;
; Late Slack - Fit Attempt 1          ; 2147483639 ;
; Late Wire Use - Fit Attempt 1       ; 0          ;
; Time - Fit Attempt 1                ; 0          ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.016      ;
+-------------------------------------+------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Fri Jun 15 17:03:48 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off ELEC -c ELEC
Info: Selected device EP1C3T144C8 for design "ELEC"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP1C6T144C8 is compatible
Info: No exact pin location assignment(s) for 4 pins of 5 total pins
    Info: Pin Q not assigned to an exact location on the device
    Info: Pin D not assigned to an exact location on the device
    Info: Pin PRN not assigned to an exact location on the device
    Info: Pin CLRN not assigned to an exact location on the device
Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing: elapsed time is 00:00:00
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 4 (unused VREF, 3.30 VCCIO, 3 input, 1 output, 0 bidirectional)
        Info: I/O standards used: LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  20 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  25 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available
Warning: Ignored locations or region assignments to the following nodes
    Warning: Node "DATA_BCD[0]" is assigned to location or region, but does not exist in design
    Warning: Node "DATA_BCD[1]" is assigned to location or region, but does not exist in design
    Warning: Node "DATA_BCD[2]" is assigned to location or region, but does not exist in design
    Warning: Node "DATA_BCD[3]" is assigned to location or region, but does not exist in design
    Warning: Node "DATA_BCD[4]" is assigned to location or region, but does not exist in design
    Warning: Node "DATA_BCD[5]" is assigned to location or region, but does not exist in design
    Warning: Node "DATA_BCD[6]" is assigned to location or region, but does not exist in design
    Warning: Node "DATA_BCD[7]" is assigned to location or region, but does not exist in design
    Warning: Node "KEY_IN[0]" is assigned to location or region, but does not exist in design
    Warning: Node "KEY_IN[1]" is assigned to location or region, but does not exist in design
    Warning: Node "KEY_IN[2]" is assigned to location or region, but does not exist in design
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Quartus II Fitter was successful. 0 errors, 12 warnings
    Info: Processing ended: Fri Jun 15 17:03:51 2007
    Info: Elapsed time: 00:00:03


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in C:/Documents and Settings/user/桌面/ELEC/ELEC.fit.smsg.