fp.vhd

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--FP.VHD
LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY FP IS
  PORT(CLK: IN STD_LOGIC; 
	   CLK_1K: OUT STD_LOGIC); 
	END ENTITY FP ; 
ARCHITECTURE KILLONESELF OF FP IS
SIGNAL TEMP:STD_LOGIC_VECTOR(15 DOWNTO 0);
  BEGIN
  PROCESS (CLK)
    BEGIN
	  IF CLK'EVENT AND CLK='1' THEN
	      TEMP<=TEMP+1;
   END IF ; 
  END PROCESS ; 
   CLK_1K<=TEMP(15);
END ARCHITECTURE KILLONESELF;