📄 play.tan.rpt
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; N/A ; 70.92 MHz ( period = 14.100 ns ) ; counter4Hz[2] ; counter4Hz[22] ; sys_CLK ; sys_CLK ; None ; None ; 9.600 ns ;
; N/A ; 70.92 MHz ( period = 14.100 ns ) ; counter4Hz[1] ; counter4Hz[22] ; sys_CLK ; sys_CLK ; None ; None ; 9.600 ns ;
; N/A ; 71.43 MHz ( period = 14.000 ns ) ; counter4Hz[23] ; counter4Hz[18] ; sys_CLK ; sys_CLK ; None ; None ; 9.500 ns ;
; N/A ; 71.43 MHz ( period = 14.000 ns ) ; counter4Hz[22] ; counter4Hz[19] ; sys_CLK ; sys_CLK ; None ; None ; 9.500 ns ;
; N/A ; 71.43 MHz ( period = 14.000 ns ) ; counter4Hz[21] ; counter4Hz[19] ; sys_CLK ; sys_CLK ; None ; None ; 9.500 ns ;
; N/A ; 71.43 MHz ( period = 14.000 ns ) ; counter4Hz[20] ; counter4Hz[19] ; sys_CLK ; sys_CLK ; None ; None ; 9.500 ns ;
; N/A ; 71.43 MHz ( period = 14.000 ns ) ; counter4Hz[19] ; counter4Hz[19] ; sys_CLK ; sys_CLK ; None ; None ; 9.500 ns ;
; N/A ; 71.43 MHz ( period = 14.000 ns ) ; counter4Hz[18] ; counter4Hz[19] ; sys_CLK ; sys_CLK ; None ; None ; 9.500 ns ;
; N/A ; 71.43 MHz ( period = 14.000 ns ) ; counter4Hz[17] ; counter4Hz[19] ; sys_CLK ; sys_CLK ; None ; None ; 9.500 ns ;
; N/A ; 71.43 MHz ( period = 14.000 ns ) ; counter4Hz[16] ; counter4Hz[19] ; sys_CLK ; sys_CLK ; None ; None ; 9.500 ns ;
; N/A ; 71.43 MHz ( period = 14.000 ns ) ; counter4Hz[23] ; counter4Hz[19] ; sys_CLK ; sys_CLK ; None ; None ; 9.500 ns ;
; N/A ; 71.43 MHz ( period = 14.000 ns ) ; counter4Hz[22] ; counter4Hz[20] ; sys_CLK ; sys_CLK ; None ; None ; 9.500 ns ;
; N/A ; 71.43 MHz ( period = 14.000 ns ) ; counter4Hz[21] ; counter4Hz[20] ; sys_CLK ; sys_CLK ; None ; None ; 9.500 ns ;
; N/A ; 71.43 MHz ( period = 14.000 ns ) ; counter4Hz[20] ; counter4Hz[20] ; sys_CLK ; sys_CLK ; None ; None ; 9.500 ns ;
; N/A ; 71.43 MHz ( period = 14.000 ns ) ; counter4Hz[19] ; counter4Hz[20] ; sys_CLK ; sys_CLK ; None ; None ; 9.500 ns ;
; N/A ; 71.43 MHz ( period = 14.000 ns ) ; counter4Hz[18] ; counter4Hz[20] ; sys_CLK ; sys_CLK ; None ; None ; 9.500 ns ;
; N/A ; 71.43 MHz ( period = 14.000 ns ) ; counter4Hz[17] ; counter4Hz[20] ; sys_CLK ; sys_CLK ; None ; None ; 9.500 ns ;
; N/A ; 71.43 MHz ( period = 14.000 ns ) ; counter4Hz[16] ; counter4Hz[20] ; sys_CLK ; sys_CLK ; None ; None ; 9.500 ns ;
; N/A ; 71.43 MHz ( period = 14.000 ns ) ; counter4Hz[23] ; counter4Hz[20] ; sys_CLK ; sys_CLK ; None ; None ; 9.500 ns ;
; N/A ; 71.43 MHz ( period = 14.000 ns ) ; counter4Hz[22] ; counter4Hz[22] ; sys_CLK ; sys_CLK ; None ; None ; 9.500 ns ;
; N/A ; 71.43 MHz ( period = 14.000 ns ) ; counter4Hz[21] ; counter4Hz[22] ; sys_CLK ; sys_CLK ; None ; None ; 9.500 ns ;
; N/A ; 71.43 MHz ( period = 14.000 ns ) ; counter4Hz[20] ; counter4Hz[22] ; sys_CLK ; sys_CLK ; None ; None ; 9.500 ns ;
; N/A ; 71.43 MHz ( period = 14.000 ns ) ; counter4Hz[19] ; counter4Hz[22] ; sys_CLK ; sys_CLK ; None ; None ; 9.500 ns ;
; N/A ; 71.43 MHz ( period = 14.000 ns ) ; counter4Hz[18] ; counter4Hz[22] ; sys_CLK ; sys_CLK ; None ; None ; 9.500 ns ;
; N/A ; 71.43 MHz ( period = 14.000 ns ) ; counter4Hz[17] ; counter4Hz[22] ; sys_CLK ; sys_CLK ; None ; None ; 9.500 ns ;
; N/A ; 71.43 MHz ( period = 14.000 ns ) ; counter4Hz[16] ; counter4Hz[22] ; sys_CLK ; sys_CLK ; None ; None ; 9.500 ns ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ;
+-----------------------------------------+-----------------------------------------------------+----------------+----------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+-----------------------------------------------------------------+
; tco ;
+-------+--------------+------------+--------+-------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+--------+-------+------------+
; N/A ; None ; 6.600 ns ; audiof ; audio ; sys_CLK ;
+-------+--------------+------------+--------+-------+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
Info: Processing started: Fri Jul 06 00:18:47 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off play -c play
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "sys_CLK" is an undefined clock
Info: Clock "sys_CLK" has Internal fmax of 70.92 MHz between source register "counter4Hz[0]" and destination register "counter4Hz[9]" (period= 14.1 ns)
Info: + Longest register to register delay is 9.600 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC99; Fanout = 39; REG Node = 'counter4Hz[0]'
Info: 2: + IC(2.700 ns) + CELL(3.800 ns) = 6.500 ns; Loc. = SEXP97; Fanout = 11; COMB Node = 'reduce_nor~1sexp'
Info: 3: + IC(0.000 ns) + CELL(3.100 ns) = 9.600 ns; Loc. = LC102; Fanout = 30; REG Node = 'counter4Hz[9]'
Info: Total cell delay = 6.900 ns ( 71.88 % )
Info: Total interconnect delay = 2.700 ns ( 28.13 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "sys_CLK" to destination register is 3.400 ns
Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 25; CLK Node = 'sys_CLK'
Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC102; Fanout = 30; REG Node = 'counter4Hz[9]'
Info: Total cell delay = 3.400 ns ( 100.00 % )
Info: - Longest clock path from clock "sys_CLK" to source register is 3.400 ns
Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 25; CLK Node = 'sys_CLK'
Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC99; Fanout = 39; REG Node = 'counter4Hz[0]'
Info: Total cell delay = 3.400 ns ( 100.00 % )
Info: + Micro clock to output delay of source is 1.600 ns
Info: + Micro setup delay of destination is 2.900 ns
Info: tco from clock "sys_CLK" to destination pin "audio" through register "audiof" is 6.600 ns
Info: + Longest clock path from clock "sys_CLK" to source register is 3.400 ns
Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 25; CLK Node = 'sys_CLK'
Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC105; Fanout = 2; REG Node = 'audiof'
Info: Total cell delay = 3.400 ns ( 100.00 % )
Info: + Micro clock to output delay of source is 1.600 ns
Info: + Longest register to pin delay is 1.600 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC105; Fanout = 2; REG Node = 'audiof'
Info: 2: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_69; Fanout = 0; PIN Node = 'audio'
Info: Total cell delay = 1.600 ns ( 100.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Fri Jul 06 00:18:48 2007
Info: Elapsed time: 00:00:03
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