adc.map.rpt

通过VERILOG HDL语言使用CPLD连接PS2键盘.

; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                      ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                    ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                    ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                  ;
+------------------------+-------------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_add_sub:add_rtl_3 ;
+------------------------+-------------+---------------------------------+
; Parameter Name         ; Value       ; Type                            ;
+------------------------+-------------+---------------------------------+
; LPM_WIDTH              ; 4           ; Untyped                         ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                         ;
; LPM_DIRECTION          ; ADD         ; Untyped                         ;
; ONE_INPUT_IS_CONSTANT  ; NO          ; Untyped                         ;
; LPM_PIPELINE           ; 0           ; Untyped                         ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                         ;
; REGISTERED_AT_END      ; 0           ; Untyped                         ;
; OPTIMIZE_FOR_SPEED     ; 9           ; Untyped                         ;
; USE_CS_BUFFERS         ; 1           ; Untyped                         ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                         ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH              ;
; DEVICE_FAMILY          ; MAX3000A    ; Untyped                         ;
; USE_WYS                ; OFF         ; Untyped                         ;
; STYLE                  ; FAST        ; Untyped                         ;
; CBXI_PARAMETER         ; add_sub_djh ; Untyped                         ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                      ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                    ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                    ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                  ;
+------------------------+-------------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_add_sub:add_rtl_4 ;
+------------------------+-------------+---------------------------------+
; Parameter Name         ; Value       ; Type                            ;
+------------------------+-------------+---------------------------------+
; LPM_WIDTH              ; 4           ; Untyped                         ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                         ;
; LPM_DIRECTION          ; ADD         ; Untyped                         ;
; ONE_INPUT_IS_CONSTANT  ; NO          ; Untyped                         ;
; LPM_PIPELINE           ; 0           ; Untyped                         ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                         ;
; REGISTERED_AT_END      ; 0           ; Untyped                         ;
; OPTIMIZE_FOR_SPEED     ; 9           ; Untyped                         ;
; USE_CS_BUFFERS         ; 1           ; Untyped                         ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                         ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH              ;
; DEVICE_FAMILY          ; MAX3000A    ; Untyped                         ;
; USE_WYS                ; OFF         ; Untyped                         ;
; STYLE                  ; FAST        ; Untyped                         ;
; CBXI_PARAMETER         ; add_sub_djh ; Untyped                         ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                      ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                    ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                    ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                  ;
+------------------------+-------------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/altera/quartus50/ADC0804/adc.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
    Info: Processing started: Thu Jul 05 23:21:05 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adc -c adc
Info: Found 1 design units, including 1 entities, in source file adc.v
    Info: Found entity 1: adc
Info: Elaborating entity "adc" for the top level hierarchy
Warning: Verilog HDL assignment warning at adc.v(35): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at adc.v(39): truncated value with size 32 to match size of target (12)
Warning: Verilog HDL assignment warning at adc.v(40): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at adc.v(45): truncated value with size 32 to match size of target (5)
Warning: Verilog HDL assignment warning at adc.v(49): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at adc.v(52): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL Always Construct warning at adc.v(62): variable "nop1" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Verilog HDL Always Construct warning at adc.v(84): variable "nop1" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Verilog HDL assignment warning at adc.v(111): truncated value with size 32 to match size of target (12)
Warning: Verilog HDL assignment warning at adc.v(115): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at adc.v(120): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at adc.v(134): truncated value with size 32 to match size of target (3)
Warning: Verilog HDL Always Construct warning at adc.v(135): variable "count" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Verilog HDL assignment warning at adc.v(139): truncated value with size 32 to match size of target (3)
Warning: Verilog HDL Always Construct warning at adc.v(140): variable "count" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Verilog HDL assignment warning at adc.v(144): truncated value with size 32 to match size of target (3)
Warning: Verilog HDL Always Construct warning at adc.v(145): variable "count" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: (10270) Verilog HDL statement warning at adc.v(131): incomplete Case Statement has no default case item
Warning: Verilog HDL Always Construct warning at adc.v(129): variable "weixuann" may not be assigned a new value in every possible path through the Always Construct.  Variable "weixuann" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL Always Construct warning at adc.v(129): variable "shuma" may not be assigned a new value in every possible path through the Always Construct.  Variable "shuma" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: (10270) Verilog HDL statement warning at adc.v(151): incomplete Case Statement has no default case item
Warning: Verilog HDL Always Construct warning at adc.v(149): variable "lddat_reg" may not be assigned a new value in every possible path through the Always Construct.  Variable "lddat_reg" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: "count1[0]~10"
Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/look_add.tdf
    Info: Found entity 1: look_add
Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: State machine "|adc|state1" contains 4 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine "|adc|state1"
Info: Encoding result for state machine "|adc|state1"
    Info: Completed encoding using 2 state bits
        Info: Encoded state bit "state1~8"
        Info: Encoded state bit "state1~7"
    Info: State "|adc|state1.st0" uses code string "00"
    Info: State "|adc|state1.st2" uses code string "10"
    Info: State "|adc|state1.st1" uses code string "01"
    Info: State "|adc|state1.st3" uses code string "11"
Info: Ignored 24 buffer(s)
    Info: Ignored 24 SOFT buffer(s)
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "lddat[7]" stuck at VCC
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "clk" to global clock signal
Info: Implemented 128 device resources after synthesis - the final resource count might be different
    Info: Implemented 10 input pins
    Info: Implemented 14 output pins
    Info: Implemented 88 macrocells
    Info: Implemented 16 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 24 warnings
    Info: Processing ended: Thu Jul 05 23:21:16 2007
    Info: Elapsed time: 00:00:12