📄 adc.tan.qmsg
字号:
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "weixuann\[0\]~29 " "Info: Node \"weixuann\[0\]~29\"" { } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 14 -1 0 } } } 0} } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 14 -1 0 } } } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 4 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register count\[5\] register count\[1\] 46.95 MHz 21.3 ns Internal " "Info: Clock \"clk\" has Internal fmax of 46.95 MHz between source register \"count\[5\]\" and destination register \"count\[1\]\" (period= 21.3 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.800 ns + Longest register register " "Info: + Longest register to register delay is 16.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[5\] 1 REG LC21 35 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC21; Fanout = 35; REG Node = 'count\[5\]'" { } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "" { count[5] } "NODE_NAME" } "" } } { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 24 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(3.800 ns) 6.600 ns LessThan~621 2 COMB SEXP49 5 " "Info: 2: + IC(2.800 ns) + CELL(3.800 ns) = 6.600 ns; Loc. = SEXP49; Fanout = 5; COMB Node = 'LessThan~621'" { } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "6.600 ns" { count[5] LessThan~621 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.400 ns) 11.000 ns LessThan~631 3 COMB LC52 19 " "Info: 3: + IC(0.000 ns) + CELL(4.400 ns) = 11.000 ns; Loc. = LC52; Fanout = 19; COMB Node = 'LessThan~631'" { } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "4.400 ns" { LessThan~621 LessThan~631 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(3.100 ns) 16.800 ns count\[1\] 4 REG LC34 30 " "Info: 4: + IC(2.700 ns) + CELL(3.100 ns) = 16.800 ns; Loc. = LC34; Fanout = 30; REG Node = 'count\[1\]'" { } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "5.800 ns" { LessThan~631 count[1] } "NODE_NAME" } "" } } { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 24 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.300 ns 67.26 % " "Info: Total cell delay = 11.300 ns ( 67.26 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.500 ns 32.74 % " "Info: Total interconnect delay = 5.500 ns ( 32.74 % )" { } { } 0} } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "16.800 ns" { count[5] LessThan~621 LessThan~631 count[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "16.800 ns" { count[5] LessThan~621 LessThan~631 count[1] } { 0.000ns 2.800ns 0.000ns 2.700ns } { 0.000ns 3.800ns 4.400ns 3.100ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.400 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clk 1 CLK PIN_87 41 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 41; CLK Node = 'clk'" { } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "" { clk } "NODE_NAME" } "" } } { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 4 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns count\[1\] 2 REG LC34 30 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC34; Fanout = 30; REG Node = 'count\[1\]'" { } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "0.900 ns" { clk count[1] } "NODE_NAME" } "" } } { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 24 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns 100.00 % " "Info: Total cell delay = 3.400 ns ( 100.00 % )" { } { } 0} } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "3.400 ns" { clk count[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clk clk~out count[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.400 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clk 1 CLK PIN_87 41 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 41; CLK Node = 'clk'" { } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "" { clk } "NODE_NAME" } "" } } { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 4 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns count\[5\] 2 REG LC21 35 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC21; Fanout = 35; REG Node = 'count\[5\]'" { } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "0.900 ns" { clk count[5] } "NODE_NAME" } "" } } { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 24 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns 100.00 % " "Info: Total cell delay = 3.400 ns ( 100.00 % )" { } { } 0} } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "3.400 ns" { clk count[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clk clk~out count[5] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } } 0} } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "3.400 ns" { clk count[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clk clk~out count[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "3.400 ns" { clk count[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clk clk~out count[5] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" { } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 24 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" { } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 24 -1 0 } } } 0} } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "16.800 ns" { count[5] LessThan~621 LessThan~631 count[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "16.800 ns" { count[5] LessThan~621 LessThan~631 count[1] } { 0.000ns 2.800ns 0.000ns 2.700ns } { 0.000ns 3.800ns 4.400ns 3.100ns } } } { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "3.400 ns" { clk count[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clk clk~out count[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "3.400 ns" { clk count[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clk clk~out count[5] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "shuchuu\[0\] shuchu\[0\] clk 6.600 ns register " "Info: tsu for register \"shuchuu\[0\]\" (data pin = \"shuchu\[0\]\", clock pin = \"clk\") is 6.600 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.100 ns + Longest pin register " "Info: + Longest pin to register delay is 7.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns shuchu\[0\] 1 PIN PIN_45 1 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_45; Fanout = 1; PIN Node = 'shuchu\[0\]'" { } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "" { shuchu[0] } "NODE_NAME" } "" } } { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 2 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(3.100 ns) 7.100 ns shuchuu\[0\] 2 REG LC81 1 " "Info: 2: + IC(2.600 ns) + CELL(3.100 ns) = 7.100 ns; Loc. = LC81; Fanout = 1; REG Node = 'shuchuu\[0\]'" { } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "5.700 ns" { shuchu[0] shuchuu[0] } "NODE_NAME" } "" } } { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 13 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.500 ns 63.38 % " "Info: Total cell delay = 4.500 ns ( 63.38 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns 36.62 % " "Info: Total interconnect delay = 2.600 ns ( 36.62 % )" { } { } 0} } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "7.100 ns" { shuchu[0] shuchuu[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.100 ns" { shuchu[0] shuchu[0]~out shuchuu[0] } { 0.000ns 0.000ns 2.600ns } { 0.000ns 1.400ns 3.100ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" { } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 13 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.400 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clk 1 CLK PIN_87 41 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 41; CLK Node = 'clk'" { } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "" { clk } "NODE_NAME" } "" } } { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 4 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns shuchuu\[0\] 2 REG LC81 1 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC81; Fanout = 1; REG Node = 'shuchuu\[0\]'" { } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "0.900 ns" { clk shuchuu[0] } "NODE_NAME" } "" } } { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 13 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns 100.00 % " "Info: Total cell delay = 3.400 ns ( 100.00 % )" { } { } 0} } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "3.400 ns" { clk shuchuu[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clk clk~out shuchuu[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } } 0} } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "7.100 ns" { shuchu[0] shuchuu[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.100 ns" { shuchu[0] shuchu[0]~out shuchuu[0] } { 0.000ns 0.000ns 2.600ns } { 0.000ns 1.400ns 3.100ns } } } { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "3.400 ns" { clk shuchuu[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clk clk~out shuchuu[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk lddat\[3\] counter\[11\] 35.000 ns register " "Info: tco from clock \"clk\" to destination pin \"lddat\[3\]\" through register \"counter\[11\]\" is 35.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.400 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clk 1 CLK PIN_87 41 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 41; CLK Node = 'clk'" { } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "" { clk } "NODE_NAME" } "" } } { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 4 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns counter\[11\] 2 REG LC114 39 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC114; Fanout = 39; REG Node = 'counter\[11\]'" { } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "0.900 ns" { clk counter[11] } "NODE_NAME" } "" } } { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 16 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns 100.00 % " "Info: Total cell delay = 3.400 ns ( 100.00 % )" { } { } 0} } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "3.400 ns" { clk counter[11] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clk clk~out counter[11] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" { } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 16 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "30.000 ns + Longest register pin " "Info: + Longest register to pin delay is 30.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter\[11\] 1 REG LC114 39 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC114; Fanout = 39; REG Node = 'counter\[11\]'" { } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "" { counter[11] } "NODE_NAME" } "" } } { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 16 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(4.400 ns) 7.200 ns Select~389 2 COMB LC37 3 " "Info: 2: + IC(2.800 ns) + CELL(4.400 ns) = 7.200 ns; Loc. = LC37; Fanout = 3; COMB Node = 'Select~389'" { } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "7.200 ns" { counter[11] Select~389 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 14.200 ns shuma\[0\]~79 3 COMB LOOP LC122 21 " "Info: 3: + IC(0.000 ns) + CELL(7.000 ns) = 14.200 ns; Loc. = LC122; Fanout = 21; COMB LOOP Node = 'shuma\[0\]~79'" { { "Info" "ITDB_PART_OF_SCC" "shuma\[0\]~79 LC122 " "Info: Loc. = LC122; Node \"shuma\[0\]~79\"" { } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "" { shuma[0]~79 } "NODE_NAME" } "" } } } 0} } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "" { shuma[0]~79 } "NODE_NAME" } "" } } { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 18 -1 0 } } { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "7.000 ns" { Select~389 shuma[0]~79 } "NODE_NAME" } "" } } { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 18 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(4.400 ns) 21.300 ns lddat_reg~208 4 COMB LC124 6 " "Info: 4: + IC(2.700 ns) + CELL(4.400 ns) = 21.300 ns; Loc. = LC124; Fanout = 6; COMB Node = 'lddat_reg~208'" { } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "7.100 ns" { shuma[0]~79 lddat_reg~208 } "NODE_NAME" } "" } } { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 15 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.100 ns) 28.400 ns lddat_reg\[3\]~267 5 COMB LOOP LC16 4 " "Info: 5: + IC(0.000 ns) + CELL(7.100 ns) = 28.400 ns; Loc. = LC16; Fanout = 4; COMB LOOP Node = 'lddat_reg\[3\]~267'" { { "Info" "ITDB_PART_OF_SCC" "shuma\[1\]~67 LC118 " "Info: Loc. = LC118; Node \"shuma\[1\]~67\"" { } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "" { shuma[1]~67 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_PART_OF_SCC" "shuma\[2\]~71 LC119 " "Info: Loc. = LC119; Node \"shuma\[2\]~71\"" { } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "" { shuma[2]~71 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_PART_OF_SCC" "shuma\[3\]~75 LC120 " "Info: Loc. = LC120; Node \"shuma\[3\]~75\"" { } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "" { shuma[3]~75 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_PART_OF_SCC" "shuma\[0\]~79 LC122 " "Info: Loc. = LC122; Node \"shuma\[0\]~79\"" { } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "" { shuma[0]~79 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_PART_OF_SCC" "lddat_reg\[3\]~267 LC16 " "Info: Loc. = LC16; Node \"lddat_reg\[3\]~267\"" { } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "" { lddat_reg[3]~267 } "NODE_NAME" } "" } } } 0} } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "" { shuma[1]~67 } "NODE_NAME" } "" } } { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 18 -1 0 } } { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "" { shuma[2]~71 } "NODE_NAME" } "" } } { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 18 -1 0 } } { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "" { shuma[3]~75 } "NODE_NAME" } "" } } { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 18 -1 0 } } { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "" { shuma[0]~79 } "NODE_NAME" } "" } } { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 18 -1 0 } } { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "" { lddat_reg[3]~267 } "NODE_NAME" } "" } } { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 15 -1 0 } } { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "7.100 ns" { lddat_reg~208 lddat_reg[3]~267 } "NODE_NAME" } "" } } { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 15 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 30.000 ns lddat\[3\] 6 PIN PIN_92 0 " "Info: 6: + IC(0.000 ns) + CELL(1.600 ns) = 30.000 ns; Loc. = PIN_92; Fanout = 0; PIN Node = 'lddat\[3\]'" { } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "1.600 ns" { lddat_reg[3]~267 lddat[3] } "NODE_NAME" } "" } } { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 3 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "24.500 ns 81.67 % " "Info: Total cell delay = 24.500 ns ( 81.67 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.500 ns 18.33 % " "Info: Total interconnect delay = 5.500 ns ( 18.33 % )" { } { } 0} } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "30.000 ns" { counter[11] Select~389 shuma[0]~79 lddat_reg~208 lddat_reg[3]~267 lddat[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "30.000 ns" { counter[11] Select~389 shuma[0]~79 lddat_reg~208 lddat_reg[3]~267 lddat[3] } { 0.000ns 2.800ns 0.000ns 2.700ns 0.000ns 0.000ns } { 0.000ns 4.400ns 7.000ns 4.400ns 7.100ns 1.600ns } } } } 0} } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "3.400 ns" { clk counter[11] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clk clk~out counter[11] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "30.000 ns" { counter[11] Select~389 shuma[0]~79 lddat_reg~208 lddat_reg[3]~267 lddat[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "30.000 ns" { counter[11] Select~389 shuma[0]~79 lddat_reg~208 lddat_reg[3]~267 lddat[3] } { 0.000ns 2.800ns 0.000ns 2.700ns 0.000ns 0.000ns } { 0.000ns 4.400ns 7.000ns 4.400ns 7.100ns 1.600ns } } } } 0}
{ "Info" "ITDB_TH_RESULT" "shuchuu\[0\] shuchu\[0\] clk -2.400 ns register " "Info: th for register \"shuchuu\[0\]\" (data pin = \"shuchu\[0\]\", clock pin = \"clk\") is -2.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.400 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns clk 1 CLK PIN_87 41 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 41; CLK Node = 'clk'" { } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "" { clk } "NODE_NAME" } "" } } { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 4 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns shuchuu\[0\] 2 REG LC81 1 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC81; Fanout = 1; REG Node = 'shuchuu\[0\]'" { } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "0.900 ns" { clk shuchuu[0] } "NODE_NAME" } "" } } { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 13 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns 100.00 % " "Info: Total cell delay = 3.400 ns ( 100.00 % )" { } { } 0} } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "3.400 ns" { clk shuchuu[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clk clk~out shuchuu[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" { } { { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 13 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.100 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns shuchu\[0\] 1 PIN PIN_45 1 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_45; Fanout = 1; PIN Node = 'shuchu\[0\]'" { } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "" { shuchu[0] } "NODE_NAME" } "" } } { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 2 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(3.100 ns) 7.100 ns shuchuu\[0\] 2 REG LC81 1 " "Info: 2: + IC(2.600 ns) + CELL(3.100 ns) = 7.100 ns; Loc. = LC81; Fanout = 1; REG Node = 'shuchuu\[0\]'" { } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "5.700 ns" { shuchu[0] shuchuu[0] } "NODE_NAME" } "" } } { "adc.v" "" { Text "C:/altera/quartus50/ADC0804/adc.v" 13 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.500 ns 63.38 % " "Info: Total cell delay = 4.500 ns ( 63.38 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns 36.62 % " "Info: Total interconnect delay = 2.600 ns ( 36.62 % )" { } { } 0} } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "7.100 ns" { shuchu[0] shuchuu[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.100 ns" { shuchu[0] shuchu[0]~out shuchuu[0] } { 0.000ns 0.000ns 2.600ns } { 0.000ns 1.400ns 3.100ns } } } } 0} } { { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "3.400 ns" { clk shuchuu[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clk clk~out shuchuu[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } } { "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" "" { Report "C:/altera/quartus50/ADC0804/db/adc_cmp.qrpt" Compiler "adc" "UNKNOWN" "V1" "C:/altera/quartus50/ADC0804/db/adc.quartus_db" { Floorplan "C:/altera/quartus50/ADC0804/" "" "7.100 ns" { shuchu[0] shuchuu[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.100 ns" { shuchu[0] shuchu[0]~out shuchuu[0] } { 0.000ns 0.000ns 2.600ns } { 0.000ns 1.400ns 3.100ns } } } } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 05 23:21:32 2007 " "Info: Processing ended: Thu Jul 05 23:21:32 2007" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" { } { } 0} } { } 0}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -