hongwai.map.eqn

通过VERILOG HDL语言使用CPLD连接PS2键盘.

-- Copyright (C) 1991-2005 Altera Corporation
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-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
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-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L2 is jie~8
A1L2_or_out = !jie;
A1L2 = A1L2_or_out;


--A1L3 is jie~10
A1L3_or_out = !jie;
A1L3 = A1L3_or_out;


--A1L4 is jie~12
A1L4_or_out = !jie;
A1L4 = A1L4_or_out;


--A1L5 is jie~14
A1L5_or_out = !jie;
A1L5 = A1L5_or_out;


--~VCC~0 is ~VCC~0
~VCC~0_or_out = GND;
~VCC~0 = !(~VCC~0_or_out);


--~VCC~1 is ~VCC~1
~VCC~1_or_out = GND;
~VCC~1 = !(~VCC~1_or_out);


--~VCC~2 is ~VCC~2
~VCC~2_or_out = GND;
~VCC~2 = !(~VCC~2_or_out);


--~VCC~3 is ~VCC~3
~VCC~3_or_out = GND;
~VCC~3 = !(~VCC~3_or_out);


--jie is jie
--operation mode is input

jie = INPUT();


--led[1] is led[1]
--operation mode is output

led[1] = OUTPUT(~VCC~0);


--led[3] is led[3]
--operation mode is output

led[3] = OUTPUT(~VCC~1);


--led[5] is led[5]
--operation mode is output

led[5] = OUTPUT(~VCC~2);


--led[7] is led[7]
--operation mode is output

led[7] = OUTPUT(~VCC~3);


--led[0] is led[0]
--operation mode is output

led[0] = OUTPUT(A1L4);


--led[2] is led[2]
--operation mode is output

led[2] = OUTPUT(A1L3);


--led[4] is led[4]
--operation mode is output

led[4] = OUTPUT(A1L2);


--led[6] is led[6]
--operation mode is output

led[6] = OUTPUT(A1L5);