jishu2.map.rpt

通过VERILOG HDL语言使用CPLD连接PS2键盘.

+----------------------+----------------------+
; Logic cells          ; 66                   ;
; Total registers      ; 32                   ;
; I/O pins             ; 15                   ;
; Shareable expanders  ; 11                   ;
; Parallel expanders   ; 6                    ;
; Maximum fan-out node ; counta[11]           ;
; Maximum fan-out      ; 53                   ;
; Total fan-out        ; 1062                 ;
; Average fan-out      ; 11.54                ;
+----------------------+----------------------+


+---------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                             ;
+------------------------------------+------------+------+------------------------------------------------------------------------+
; Compilation Hierarchy Node         ; Macrocells ; Pins ; Full Hierarchy Name                                                    ;
+------------------------------------+------------+------+------------------------------------------------------------------------+
; |jishu2                            ; 66         ; 15   ; |jishu2                                                                ;
;    |lpm_add_sub:add_rtl_0|         ; 5          ; 0    ; |jishu2|lpm_add_sub:add_rtl_0                                          ;
;       |addcore:adder[3]|           ; 5          ; 0    ; |jishu2|lpm_add_sub:add_rtl_0|addcore:adder[3]                         ;
;          |a_csnbuffer:result_node| ; 5          ; 0    ; |jishu2|lpm_add_sub:add_rtl_0|addcore:adder[3]|a_csnbuffer:result_node ;
+------------------------------------+------------+------+------------------------------------------------------------------------+


+---------------------------------------------------+
; User-Specified and Inferred Latches               ;
+-----------------------------------------------+---+
; Latch Name                                    ;   ;
+-----------------------------------------------+---+
; duanreg[0]                                    ;   ;
; duanreg[1]                                    ;   ;
; duanreg[2]                                    ;   ;
; duanreg[3]                                    ;   ;
; duanreg[4]                                    ;   ;
; duanreg[5]                                    ;   ;
; duanreg[6]                                    ;   ;
; Number of user-specified and inferred latches ; 7 ;
+-----------------------------------------------+---+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_add_sub:add_rtl_0 ;
+------------------------+-------------+---------------------------------+
; Parameter Name         ; Value       ; Type                            ;
+------------------------+-------------+---------------------------------+
; LPM_WIDTH              ; 32          ; Untyped                         ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                         ;
; LPM_DIRECTION          ; ADD         ; Untyped                         ;
; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                         ;
; LPM_PIPELINE           ; 0           ; Untyped                         ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                         ;
; REGISTERED_AT_END      ; 0           ; Untyped                         ;
; OPTIMIZE_FOR_SPEED     ; 9           ; Untyped                         ;
; USE_CS_BUFFERS         ; 1           ; Untyped                         ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                         ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH              ;
; DEVICE_FAMILY          ; MAX3000A    ; Untyped                         ;
; USE_WYS                ; OFF         ; Untyped                         ;
; STYLE                  ; FAST        ; Untyped                         ;
; CBXI_PARAMETER         ; add_sub_ioh ; Untyped                         ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                      ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                    ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                    ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                  ;
+------------------------+-------------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/altera/quartus50/0-99COUNTER/jishu2.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
    Info: Processing started: Thu Jul 05 22:49:29 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off jishu2 -c jishu2
Info: Found 1 design units, including 1 entities, in source file jishu2.v
    Info: Found entity 1: jishu2
Info: Elaborating entity "jishu2" for the top level hierarchy
Warning: Verilog HDL assignment warning at jishu2.v(15): truncated value with size 32 to match size of target (4)
Warning: (10270) Verilog HDL statement warning at jishu2.v(36): incomplete Case Statement has no default case item
Warning: Verilog HDL Always Construct warning at jishu2.v(34): variable "duanreg" may not be assigned a new value in every possible path through the Always Construct.  Variable "duanreg" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/look_add.tdf
    Info: Found entity 1: look_add
Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Ignored 32 buffer(s)
    Info: Ignored 32 SOFT buffer(s)
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "duan[7]" stuck at VCC
    Warning: Pin "wei[2]" stuck at GND
    Warning: Pin "wei[3]" stuck at GND
    Warning: Pin "wei[4]" stuck at GND
    Warning: Pin "wei[5]" stuck at GND
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "clk" to global clock signal
Info: Implemented 92 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 14 output pins
    Info: Implemented 66 macrocells
    Info: Implemented 11 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings
    Info: Processing ended: Thu Jul 05 22:49:39 2007
    Info: Elapsed time: 00:00:11