jishu2.tan.rpt

通过VERILOG HDL语言使用CPLD连接PS2键盘.

; N/A   ; None         ; 20.800 ns  ; counta[30] ; duan[1] ; clk        ;
; N/A   ; None         ; 20.800 ns  ; counta[29] ; duan[1] ; clk        ;
; N/A   ; None         ; 20.800 ns  ; counta[28] ; duan[0] ; clk        ;
; N/A   ; None         ; 20.800 ns  ; counta[31] ; duan[0] ; clk        ;
; N/A   ; None         ; 20.800 ns  ; counta[30] ; duan[0] ; clk        ;
; N/A   ; None         ; 20.800 ns  ; counta[29] ; duan[0] ; clk        ;
; N/A   ; None         ; 20.700 ns  ; counta[28] ; duan[1] ; clk        ;
; N/A   ; None         ; 14.000 ns  ; counta[11] ; wei[0]  ; clk        ;
; N/A   ; None         ; 6.600 ns   ; counta[11] ; wei[1]  ; clk        ;
+-------+--------------+------------+------------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
    Info: Processing started: Thu Jul 05 22:49:54 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off jishu2 -c jishu2
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Found combinational loop of 1 nodes
    Info: Node "duanreg[6]~361"
Info: Found combinational loop of 3 nodes
    Info: Node "duanreg[5]~357"
    Info: Node "duanreg[5]~383"
    Info: Node "duanreg[5]~384"
Info: Found combinational loop of 2 nodes
    Info: Node "duanreg[4]~353"
    Info: Node "duanreg[4]~374"
Info: Found combinational loop of 2 nodes
    Info: Node "duanreg[3]~349"
    Info: Node "duanreg[3]~367"
Info: Found combinational loop of 1 nodes
    Info: Node "duanreg[2]~345"
Info: Found combinational loop of 1 nodes
    Info: Node "duanreg[1]~341"
Info: Found combinational loop of 1 nodes
    Info: Node "duanreg[0]~337"
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 53.76 MHz between source register "counta[25]" and destination register "counta[29]" (period= 18.6 ns)
    Info: + Longest register to register delay is 14.100 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC33; Fanout = 63; REG Node = 'counta[25]'
        Info: 2: + IC(3.000 ns) + CELL(1.300 ns) = 4.300 ns; Loc. = LC25; Fanout = 1; COMB Node = 'reduce_nor~14'
        Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 8.300 ns; Loc. = LC26; Fanout = 31; COMB Node = 'reduce_nor~7'
        Info: 4: + IC(2.700 ns) + CELL(3.100 ns) = 14.100 ns; Loc. = LC52; Fanout = 29; REG Node = 'counta[29]'
        Info: Total cell delay = 8.400 ns ( 59.57 % )
        Info: Total interconnect delay = 5.700 ns ( 40.43 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.400 ns
            Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 32; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC52; Fanout = 29; REG Node = 'counta[29]'
            Info: Total cell delay = 3.400 ns ( 100.00 % )
        Info: - Longest clock path from clock "clk" to source register is 3.400 ns
            Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 32; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC33; Fanout = 63; REG Node = 'counta[25]'
            Info: Total cell delay = 3.400 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.600 ns
    Info: + Micro setup delay of destination is 2.900 ns
Info: tco from clock "clk" to destination pin "duan[5]" through register "counta[26]" is 29.000 ns
    Info: + Longest clock path from clock "clk" to source register is 3.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 32; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC22; Fanout = 55; REG Node = 'counta[26]'
        Info: Total cell delay = 3.400 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.600 ns
    Info: + Longest register to pin delay is 24.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC22; Fanout = 55; REG Node = 'counta[26]'
        Info: 2: + IC(3.000 ns) + CELL(4.400 ns) = 7.400 ns; Loc. = LC6; Fanout = 30; COMB Node = 'reduce_or~736'
        Info: 3: + IC(0.000 ns) + CELL(8.000 ns) = 15.400 ns; Loc. = LC3; Fanout = 7; COMB LOOP Node = 'duanreg[5]~357'
            Info: Loc. = LC3; Node "duanreg[5]~357"
            Info: Loc. = LC2; Node "duanreg[5]~383"
            Info: Loc. = LC1; Node "duanreg[5]~384"
        Info: 4: + IC(2.600 ns) + CELL(4.400 ns) = 22.400 ns; Loc. = LC13; Fanout = 1; COMB Node = 'duanreg[5]~386'
        Info: 5: + IC(0.000 ns) + CELL(1.600 ns) = 24.000 ns; Loc. = PIN_94; Fanout = 0; PIN Node = 'duan[5]'
        Info: Total cell delay = 18.400 ns ( 76.67 % )
        Info: Total interconnect delay = 5.600 ns ( 23.33 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu Jul 05 22:49:55 2007
    Info: Elapsed time: 00:00:02