jishu2.fit.summary

通过VERILOG HDL语言使用CPLD连接PS2键盘.

Flow Status : Successful - Thu Jul 05 22:49:47 2007
Quartus II Version : 5.0 Build 168 06/22/2005 SP 1 SJ Full Version
Revision Name : jishu2
Top-level Entity Name : jishu2
Family : MAX3000A
Device : EPM3128ATC100-10
Timing Models : Final
Met timing requirements : N/A
Total macrocells : 68 / 128 ( 53 % )
Total pins : 19 / 80 ( 23 % )