📄 ps21.tan.qmsg

📁 通过VERILOG HDL语言使用CPLD连接PS2键盘.
💻 QMSG
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{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "sys_clock 57 " "Warning: Circuit may not operate. Detected 57 non-operational path(s) clocked by clock \"sys_clock\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "save_scan_code\[9\] scan_parity~reg0 sys_clock 500 ps " "Info: Found hold time violation between source  pin or register \"save_scan_code\[9\]\" and destination pin or register \"scan_parity~reg0\" for clock \"sys_clock\" (Hold time is 500 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "6.600 ns + Largest " "Info: + Largest clock skew is 6.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clock destination 16.400 ns + Longest register " "Info: + Longest clock path from clock \"sys_clock\" to destination register is 16.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns sys_clock 1 CLK PIN_87 15 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 15; CLK Node = 'sys_clock'" {  } { { "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" Compiler "ps21" "UNKNOWN" "V1" "C:/altera/quartus50/PS2SMGdispaly/db/ps21.quartus_db" { Floorplan "C:/altera/quartus50/PS2SMGdispaly/" "" "" { sys_clock } "NODE_NAME" } "" } } { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns smooth_key_clock 2 REG LC44 17 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC44; Fanout = 17; REG Node = 'smooth_key_clock'" {  } { { "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" Compiler "ps21" "UNKNOWN" "V1" "C:/altera/quartus50/PS2SMGdispaly/db/ps21.quartus_db" { Floorplan "C:/altera/quartus50/PS2SMGdispaly/" "" "2.500 ns" { sys_clock smooth_key_clock } "NODE_NAME" } "" } } { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(3.800 ns) 11.400 ns scan_end~reg0 3 REG LC33 10 " "Info: 3: + IC(2.600 ns) + CELL(3.800 ns) = 11.400 ns; Loc. = LC33; Fanout = 10; REG Node = 'scan_end~reg0'" {  } { { "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" Compiler "ps21" "UNKNOWN" "V1" "C:/altera/quartus50/PS2SMGdispaly/db/ps21.quartus_db" { Floorplan "C:/altera/quartus50/PS2SMGdispaly/" "" "6.400 ns" { smooth_key_clock scan_end~reg0 } "NODE_NAME" } "" } } { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 57 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(2.200 ns) 16.400 ns scan_parity~reg0 4 REG LC1 1 " "Info: 4: + IC(2.800 ns) + CELL(2.200 ns) = 16.400 ns; Loc. = LC1; Fanout = 1; REG Node = 'scan_parity~reg0'" {  } { { "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" Compiler "ps21" "UNKNOWN" "V1" "C:/altera/quartus50/PS2SMGdispaly/db/ps21.quartus_db" { Floorplan "C:/altera/quartus50/PS2SMGdispaly/" "" "5.000 ns" { scan_end~reg0 scan_parity~reg0 } "NODE_NAME" } "" } } { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 74 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.000 ns 67.07 % " "Info: Total cell delay = 11.000 ns ( 67.07 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.400 ns 32.93 % " "Info: Total interconnect delay = 5.400 ns ( 32.93 % )" {  } {  } 0}  } { { "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" Compiler "ps21" "UNKNOWN" "V1" "C:/altera/quartus50/PS2SMGdispaly/db/ps21.quartus_db" { Floorplan "C:/altera/quartus50/PS2SMGdispaly/" "" "16.400 ns" { sys_clock smooth_key_clock scan_end~reg0 scan_parity~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "16.400 ns" { sys_clock sys_clock~out smooth_key_clock scan_end~reg0 scan_parity~reg0 } { 0.0ns 0.0ns 0.0ns 2.6ns 2.8ns } { 0.0ns 2.5ns 2.5ns 3.8ns 2.2ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clock source 9.800 ns - Shortest register " "Info: - Shortest clock path from clock \"sys_clock\" to source register is 9.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns sys_clock 1 CLK PIN_87 15 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 15; CLK Node = 'sys_clock'" {  } { { "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" Compiler "ps21" "UNKNOWN" "V1" "C:/altera/quartus50/PS2SMGdispaly/db/ps21.quartus_db" { Floorplan "C:/altera/quartus50/PS2SMGdispaly/" "" "" { sys_clock } "NODE_NAME" } "" } } { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns smooth_key_clock 2 REG LC44 17 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC44; Fanout = 17; REG Node = 'smooth_key_clock'" {  } { { "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" Compiler "ps21" "UNKNOWN" "V1" "C:/altera/quartus50/PS2SMGdispaly/db/ps21.quartus_db" { Floorplan "C:/altera/quartus50/PS2SMGdispaly/" "" "2.500 ns" { sys_clock smooth_key_clock } "NODE_NAME" } "" } } { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(2.200 ns) 9.800 ns save_scan_code\[9\] 3 REG LC42 4 " "Info: 3: + IC(2.600 ns) + CELL(2.200 ns) = 9.800 ns; Loc. = LC42; Fanout = 4; REG Node = 'save_scan_code\[9\]'" {  } { { "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" Compiler "ps21" "UNKNOWN" "V1" "C:/altera/quartus50/PS2SMGdispaly/db/ps21.quartus_db" { Floorplan "C:/altera/quartus50/PS2SMGdispaly/" "" "4.800 ns" { smooth_key_clock save_scan_code[9] } "NODE_NAME" } "" } } { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.200 ns 73.47 % " "Info: Total cell delay = 7.200 ns ( 73.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns 26.53 % " "Info: Total interconnect delay = 2.600 ns ( 26.53 % )" {  } {  } 0}  } { { "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" Compiler "ps21" "UNKNOWN" "V1" "C:/altera/quartus50/PS2SMGdispaly/db/ps21.quartus_db" { Floorplan "C:/altera/quartus50/PS2SMGdispaly/" "" "9.800 ns" { sys_clock smooth_key_clock save_scan_code[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.800 ns" { sys_clock sys_clock~out smooth_key_clock save_scan_code[9] } { 0.0ns 0.0ns 0.0ns 2.6ns } { 0.0ns 2.5ns 2.5ns 2.2ns } } }  } 0}  } { { "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" Compiler "ps21" "UNKNOWN" "V1" "C:/altera/quartus50/PS2SMGdispaly/db/ps21.quartus_db" { Floorplan "C:/altera/quartus50/PS2SMGdispaly/" "" "16.400 ns" { sys_clock smooth_key_clock scan_end~reg0 scan_parity~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "16.400 ns" { sys_clock sys_clock~out smooth_key_clock scan_end~reg0 scan_parity~reg0 } { 0.0ns 0.0ns 0.0ns 2.6ns 2.8ns } { 0.0ns 2.5ns 2.5ns 3.8ns 2.2ns } } } { "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" Compiler "ps21" "UNKNOWN" "V1" "C:/altera/quartus50/PS2SMGdispaly/db/ps21.quartus_db" { Floorplan "C:/altera/quartus50/PS2SMGdispaly/" "" "9.800 ns" { sys_clock smooth_key_clock save_scan_code[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.800 ns" { sys_clock sys_clock~out smooth_key_clock save_scan_code[9] } { 0.0ns 0.0ns 0.0ns 2.6ns } { 0.0ns 2.5ns 2.5ns 2.2ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns - " "Info: - Micro clock to output delay of source is 1.600 ns" {  } { { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.800 ns - Shortest register register " "Info: - Shortest register to register delay is 5.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns save_scan_code\[9\] 1 REG LC42 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC42; Fanout = 4; REG Node = 'save_scan_code\[9\]'" {  } { { "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" Compiler "ps21" "UNKNOWN" "V1" "C:/altera/quartus50/PS2SMGdispaly/db/ps21.quartus_db" { Floorplan "C:/altera/quartus50/PS2SMGdispaly/" "" "" { save_scan_code[9] } "NODE_NAME" } "" } } { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(3.100 ns) 5.800 ns scan_parity~reg0 2 REG LC1 1 " "Info: 2: + IC(2.700 ns) + CELL(3.100 ns) = 5.800 ns; Loc. = LC1; Fanout = 1; REG Node = 'scan_parity~reg0'" {  } { { "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" Compiler "ps21" "UNKNOWN" "V1" "C:/altera/quartus50/PS2SMGdispaly/db/ps21.quartus_db" { Floorplan "C:/altera/quartus50/PS2SMGdispaly/" "" "5.800 ns" { save_scan_code[9] scan_parity~reg0 } "NODE_NAME" } "" } } { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 74 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.100 ns 53.45 % " "Info: Total cell delay = 3.100 ns ( 53.45 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns 46.55 % " "Info: Total interconnect delay = 2.700 ns ( 46.55 % )" {  } {  } 0}  } { { "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" Compiler "ps21" "UNKNOWN" "V1" "C:/altera/quartus50/PS2SMGdispaly/db/ps21.quartus_db" { Floorplan "C:/altera/quartus50/PS2SMGdispaly/" "" "5.800 ns" { save_scan_code[9] scan_parity~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.800 ns" { save_scan_code[9] scan_parity~reg0 } { 0.0ns 2.7ns } { 0.0ns 3.1ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 74 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 23 -1 0 } } { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 74 -1 0 } }  } 0}  } { { "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" Compiler "ps21" "UNKNOWN" "V1" "C:/altera/quartus50/PS2SMGdispaly/db/ps21.quartus_db" { Floorplan "C:/altera/quartus50/PS2SMGdispaly/" "" "16.400 ns" { sys_clock smooth_key_clock scan_end~reg0 scan_parity~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "16.400 ns" { sys_clock sys_clock~out smooth_key_clock scan_end~reg0 scan_parity~reg0 } { 0.0ns 0.0ns 0.0ns 2.6ns 2.8ns } { 0.0ns 2.5ns 2.5ns 3.8ns 2.2ns } } } { "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" Compiler "ps21" "UNKNOWN" "V1" "C:/altera/quartus50/PS2SMGdispaly/db/ps21.quartus_db" { Floorplan "C:/altera/quartus50/PS2SMGdispaly/" "" "9.800 ns" { sys_clock smooth_key_clock save_scan_code[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.800 ns" { sys_clock sys_clock~out smooth_key_clock save_scan_code[9] } { 0.0ns 0.0ns 0.0ns 2.6ns } { 0.0ns 2.5ns 2.5ns 2.2ns } } } { "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" Compiler "ps21" "UNKNOWN" "V1" "C:/altera/quartus50/PS2SMGdispaly/db/ps21.quartus_db" { Floorplan "C:/altera/quartus50/PS2SMGdispaly/" "" "5.800 ns" { save_scan_code[9] scan_parity~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.800 ns" { save_scan_code[9] scan_parity~reg0 } { 0.0ns 2.7ns } { 0.0ns 3.1ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "filter\[9\] key_clock sys_clock 6.600 ns register " "Info: tsu for register \"filter\[9\]\" (data pin = \"key_clock\", clock pin = \"sys_clock\") is 6.600 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.100 ns + Longest pin register " "Info: + Longest pin to register delay is 7.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns key_clock 1 PIN PIN_68 10 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_68; Fanout = 10; PIN Node = 'key_clock'" {  } { { "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" Compiler "ps21" "UNKNOWN" "V1" "C:/altera/quartus50/PS2SMGdispaly/db/ps21.quartus_db" { Floorplan "C:/altera/quartus50/PS2SMGdispaly/" "" "" { key_clock } "NODE_NAME" } "" } } { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(3.100 ns) 7.100 ns filter\[9\] 2 REG LC52 2 " "Info: 2: + IC(2.600 ns) + CELL(3.100 ns) = 7.100 ns; Loc. = LC52; Fanout = 2; REG Node = 'filter\[9\]'" {  } { { "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" Compiler "ps21" "UNKNOWN" "V1" "C:/altera/quartus50/PS2SMGdispaly/db/ps21.quartus_db" { Floorplan "C:/altera/quartus50/PS2SMGdispaly/" "" "5.700 ns" { key_clock filter[9] } "NODE_NAME" } "" } } { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.500 ns 63.38 % " "Info: Total cell delay = 4.500 ns ( 63.38 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns 36.62 % " "Info: Total interconnect delay = 2.600 ns ( 36.62 % )" {  } {  } 0}  } { { "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" Compiler "ps21" "UNKNOWN" "V1" "C:/altera/quartus50/PS2SMGdispaly/db/ps21.quartus_db" { Floorplan "C:/altera/quartus50/PS2SMGdispaly/" "" "7.100 ns" { key_clock filter[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.100 ns" { key_clock key_clock~out filter[9] } { 0.000ns 0.000ns 2.600ns } { 0.000ns 1.400ns 3.100ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.900 ns + " "Info: + Micro setup delay of destination is 2.900 ns" {  } { { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clock destination 3.400 ns - Shortest register " "Info: - Shortest clock path from clock \"sys_clock\" to destination register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns sys_clock 1 CLK PIN_87 15 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 15; CLK Node = 'sys_clock'" {  } { { "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" Compiler "ps21" "UNKNOWN" "V1" "C:/altera/quartus50/PS2SMGdispaly/db/ps21.quartus_db" { Floorplan "C:/altera/quartus50/PS2SMGdispaly/" "" "" { sys_clock } "NODE_NAME" } "" } } { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 3.400 ns filter\[9\] 2 REG LC52 2 " "Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 3.400 ns; Loc. = LC52; Fanout = 2; REG Node = 'filter\[9\]'" {  } { { "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" Compiler "ps21" "UNKNOWN" "V1" "C:/altera/quartus50/PS2SMGdispaly/db/ps21.quartus_db" { Floorplan "C:/altera/quartus50/PS2SMGdispaly/" "" "0.900 ns" { sys_clock filter[9] } "NODE_NAME" } "" } } { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns 100.00 % " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0}  } { { "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" Compiler "ps21" "UNKNOWN" "V1" "C:/altera/quartus50/PS2SMGdispaly/db/ps21.quartus_db" { Floorplan "C:/altera/quartus50/PS2SMGdispaly/" "" "3.400 ns" { sys_clock filter[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { sys_clock sys_clock~out filter[9] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0}  } { { "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" Compiler "ps21" "UNKNOWN" "V1" "C:/altera/quartus50/PS2SMGdispaly/db/ps21.quartus_db" { Floorplan "C:/altera/quartus50/PS2SMGdispaly/" "" "7.100 ns" { key_clock filter[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.100 ns" { key_clock key_clock~out filter[9] } { 0.000ns 0.000ns 2.600ns } { 0.000ns 1.400ns 3.100ns } } } { "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" Compiler "ps21" "UNKNOWN" "V1" "C:/altera/quartus50/PS2SMGdispaly/db/ps21.quartus_db" { Floorplan "C:/altera/quartus50/PS2SMGdispaly/" "" "3.400 ns" { sys_clock filter[9] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { sys_clock sys_clock~out filter[9] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.500ns 0.900ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "sys_clock scan_code\[6\] scan_code\[6\]~reg0 19.600 ns register " "Info: tco from clock \"sys_clock\" to destination pin \"scan_code\[6\]\" through register \"scan_code\[6\]~reg0\" is 19.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sys_clock source 16.400 ns + Longest register " "Info: + Longest clock path from clock \"sys_clock\" to source register is 16.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns sys_clock 1 CLK PIN_87 15 " "Info: 1: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = PIN_87; Fanout = 15; CLK Node = 'sys_clock'" {  } { { "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" Compiler "ps21" "UNKNOWN" "V1" "C:/altera/quartus50/PS2SMGdispaly/db/ps21.quartus_db" { Floorplan "C:/altera/quartus50/PS2SMGdispaly/" "" "" { sys_clock } "NODE_NAME" } "" } } { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 5.000 ns smooth_key_clock 2 REG LC44 17 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 5.000 ns; Loc. = LC44; Fanout = 17; REG Node = 'smooth_key_clock'" {  } { { "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" Compiler "ps21" "UNKNOWN" "V1" "C:/altera/quartus50/PS2SMGdispaly/db/ps21.quartus_db" { Floorplan "C:/altera/quartus50/PS2SMGdispaly/" "" "2.500 ns" { sys_clock smooth_key_clock } "NODE_NAME" } "" } } { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(3.800 ns) 11.400 ns scan_end~reg0 3 REG LC33 10 " "Info: 3: + IC(2.600 ns) + CELL(3.800 ns) = 11.400 ns; Loc. = LC33; Fanout = 10; REG Node = 'scan_end~reg0'" {  } { { "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" Compiler "ps21" "UNKNOWN" "V1" "C:/altera/quartus50/PS2SMGdispaly/db/ps21.quartus_db" { Floorplan "C:/altera/quartus50/PS2SMGdispaly/" "" "6.400 ns" { smooth_key_clock scan_end~reg0 } "NODE_NAME" } "" } } { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 57 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(2.200 ns) 16.400 ns scan_code\[6\]~reg0 4 REG LC29 1 " "Info: 4: + IC(2.800 ns) + CELL(2.200 ns) = 16.400 ns; Loc. = LC29; Fanout = 1; REG Node = 'scan_code\[6\]~reg0'" {  } { { "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" Compiler "ps21" "UNKNOWN" "V1" "C:/altera/quartus50/PS2SMGdispaly/db/ps21.quartus_db" { Floorplan "C:/altera/quartus50/PS2SMGdispaly/" "" "5.000 ns" { scan_end~reg0 scan_code[6]~reg0 } "NODE_NAME" } "" } } { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 74 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.000 ns 67.07 % " "Info: Total cell delay = 11.000 ns ( 67.07 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.400 ns 32.93 % " "Info: Total interconnect delay = 5.400 ns ( 32.93 % )" {  } {  } 0}  } { { "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" Compiler "ps21" "UNKNOWN" "V1" "C:/altera/quartus50/PS2SMGdispaly/db/ps21.quartus_db" { Floorplan "C:/altera/quartus50/PS2SMGdispaly/" "" "16.400 ns" { sys_clock smooth_key_clock scan_end~reg0 scan_code[6]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "16.400 ns" { sys_clock sys_clock~out smooth_key_clock scan_end~reg0 scan_code[6]~reg0 } { 0.000ns 0.000ns 0.000ns 2.600ns 2.800ns } { 0.000ns 2.500ns 2.500ns 3.800ns 2.200ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.600 ns + " "Info: + Micro clock to output delay of source is 1.600 ns" {  } { { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 74 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.600 ns + Longest register pin " "Info: + Longest register to pin delay is 1.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns scan_code\[6\]~reg0 1 REG LC29 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC29; Fanout = 1; REG Node = 'scan_code\[6\]~reg0'" {  } { { "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" Compiler "ps21" "UNKNOWN" "V1" "C:/altera/quartus50/PS2SMGdispaly/db/ps21.quartus_db" { Floorplan "C:/altera/quartus50/PS2SMGdispaly/" "" "" { scan_code[6]~reg0 } "NODE_NAME" } "" } } { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 74 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns scan_code\[6\] 2 PIN PIN_6 0 " "Info: 2: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_6; Fanout = 0; PIN Node = 'scan_code\[6\]'" {  } { { "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" Compiler "ps21" "UNKNOWN" "V1" "C:/altera/quartus50/PS2SMGdispaly/db/ps21.quartus_db" { Floorplan "C:/altera/quartus50/PS2SMGdispaly/" "" "1.600 ns" { scan_code[6]~reg0 scan_code[6] } "NODE_NAME" } "" } } { "ps21.vhd" "" { Text "C:/altera/quartus50/PS2SMGdispaly/ps21.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns 100.00 % " "Info: Total cell delay = 1.600 ns ( 100.00 % )" {  } {  } 0}  } { { "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" Compiler "ps21" "UNKNOWN" "V1" "C:/altera/quartus50/PS2SMGdispaly/db/ps21.quartus_db" { Floorplan "C:/altera/quartus50/PS2SMGdispaly/" "" "1.600 ns" { scan_code[6]~reg0 scan_code[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.600 ns" { scan_code[6]~reg0 scan_code[6] } { 0.000ns 0.000ns } { 0.000ns 1.600ns } } }  } 0}  } { { "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" Compiler "ps21" "UNKNOWN" "V1" "C:/altera/quartus50/PS2SMGdispaly/db/ps21.quartus_db" { Floorplan "C:/altera/quartus50/PS2SMGdispaly/" "" "16.400 ns" { sys_clock smooth_key_clock scan_end~reg0 scan_code[6]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "16.400 ns" { sys_clock sys_clock~out smooth_key_clock scan_end~reg0 scan_code[6]~reg0 } { 0.000ns 0.000ns 0.000ns 2.600ns 2.800ns } { 0.000ns 2.500ns 2.500ns 3.800ns 2.200ns } } } { "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" "" { Report "C:/altera/quartus50/PS2SMGdispaly/db/ps21_cmp.qrpt" Compiler "ps21" "UNKNOWN" "V1" "C:/altera/quartus50/PS2SMGdispaly/db/ps21.quartus_db" { Floorplan "C:/altera/quartus50/PS2SMGdispaly/" "" "1.600 ns" { scan_code[6]~reg0 scan_code[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.600 ns" { scan_code[6]~reg0 scan_code[6] } { 0.000ns 0.000ns } { 0.000ns 1.600ns } } }  } 0}
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