clock6.map.rpt

通过VERILOG HDL语言使用CPLD连接PS2键盘.

; Average fan-out      ; 9.16                 ;
+----------------------+----------------------+


+----------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                  ;
+----------------------------+------------+------+---------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
+----------------------------+------------+------+---------------------+
; |clock6                    ; 79         ; 15   ; |clock6             ;
+----------------------------+------------+------+---------------------+


+----------------------------------------------------+
; User-Specified and Inferred Latches                ;
+-----------------------------------------------+----+
; Latch Name                                    ;    ;
+-----------------------------------------------+----+
; lddat_reg[0]                                  ;    ;
; lddat_reg[1]                                  ;    ;
; lddat_reg[2]                                  ;    ;
; lddat_reg[3]                                  ;    ;
; lddat_reg[4]                                  ;    ;
; lddat_reg[5]                                  ;    ;
; lddat_reg[6]                                  ;    ;
; ldsel_reg[0]                                  ;    ;
; ldsel_reg[1]                                  ;    ;
; ldsel_reg[2]                                  ;    ;
; ldsel_reg[3]                                  ;    ;
; ldsel_reg[4]                                  ;    ;
; ldsel_reg[5]                                  ;    ;
; ledbuf[0]                                     ;    ;
; ledbuf[1]                                     ;    ;
; ledbuf[2]                                     ;    ;
; ledbuf[3]                                     ;    ;
; Number of user-specified and inferred latches ; 17 ;
+-----------------------------------------------+----+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_add_sub:add_rtl_0 ;
+------------------------+-------------+---------------------------------+
; Parameter Name         ; Value       ; Type                            ;
+------------------------+-------------+---------------------------------+
; LPM_WIDTH              ; 23          ; Untyped                         ;
; LPM_REPRESENTATION     ; UNSIGNED    ; Untyped                         ;
; LPM_DIRECTION          ; ADD         ; Untyped                         ;
; ONE_INPUT_IS_CONSTANT  ; YES         ; Untyped                         ;
; LPM_PIPELINE           ; 0           ; Untyped                         ;
; MAXIMIZE_SPEED         ; 5           ; Untyped                         ;
; REGISTERED_AT_END      ; 0           ; Untyped                         ;
; OPTIMIZE_FOR_SPEED     ; 9           ; Untyped                         ;
; USE_CS_BUFFERS         ; 1           ; Untyped                         ;
; CARRY_CHAIN            ; MANUAL      ; Untyped                         ;
; CARRY_CHAIN_LENGTH     ; 48          ; CARRY_CHAIN_LENGTH              ;
; DEVICE_FAMILY          ; MAX3000A    ; Untyped                         ;
; USE_WYS                ; OFF         ; Untyped                         ;
; STYLE                  ; FAST        ; Untyped                         ;
; CBXI_PARAMETER         ; add_sub_ioh ; Untyped                         ;
; AUTO_CARRY_CHAINS      ; ON          ; AUTO_CARRY                      ;
; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                    ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                    ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                  ;
+------------------------+-------------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/altera/quartus50/clock/clock6.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
    Info: Processing started: Thu Jul 05 23:27:55 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock6 -c clock6
Info: Found 1 design units, including 1 entities, in source file clock6.v
    Info: Found entity 1: clock6
Info: Elaborating entity "clock6" for the top level hierarchy
Warning: Verilog HDL assignment warning at clock6.v(13): truncated value with size 32 to match size of target (23)
Warning: Verilog HDL Always Construct warning at clock6.v(23): variable "min" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Verilog HDL Always Construct warning at clock6.v(24): variable "min" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Verilog HDL Always Construct warning at clock6.v(25): variable "min" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Verilog HDL Always Construct warning at clock6.v(26): variable "min" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Verilog HDL Always Construct warning at clock6.v(27): variable "min" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Verilog HDL Always Construct warning at clock6.v(28): variable "min" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: (10270) Verilog HDL statement warning at clock6.v(22): incomplete Case Statement has no default case item
Warning: Verilog HDL Always Construct warning at clock6.v(20): variable "ledbuf" may not be assigned a new value in every possible path through the Always Construct.  Variable "ledbuf" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: (10270) Verilog HDL statement warning at clock6.v(34): incomplete Case Statement has no default case item
Warning: Verilog HDL Always Construct warning at clock6.v(32): variable "lddat_reg" may not be assigned a new value in every possible path through the Always Construct.  Variable "lddat_reg" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: (10270) Verilog HDL statement warning at clock6.v(50): incomplete Case Statement has no default case item
Warning: Verilog HDL Always Construct warning at clock6.v(48): variable "ldsel_reg" may not be assigned a new value in every possible path through the Always Construct.  Variable "ldsel_reg" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL assignment warning at clock6.v(62): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock6.v(66): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock6.v(70): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock6.v(74): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock6.v(78): truncated value with size 32 to match size of target (4)
Warning: Verilog HDL assignment warning at clock6.v(82): truncated value with size 32 to match size of target (4)
Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/look_add.tdf
    Info: Found entity 1: look_add
Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Ignored 23 buffer(s)
    Info: Ignored 23 SOFT buffer(s)
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "lddat[7]" stuck at VCC
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "clk" to global clock signal
Info: Implemented 105 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 14 output pins
    Info: Implemented 79 macrocells
    Info: Implemented 11 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 21 warnings
    Info: Processing ended: Thu Jul 05 23:28:03 2007
    Info: Elapsed time: 00:00:09