lcd1602.map.qmsg

通过VERILOG HDL语言使用CPLD连接PS2键盘.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 05 23:57:14 2007 " "Info: Processing started: Thu Jul 05 23:57:14 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lcd1602 -c lcd1602 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lcd1602 -c lcd1602" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcd1602.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file lcd1602.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 LCD1602-Behavioral " "Info: Found design unit 1: LCD1602-Behavioral" {  } { { "lcd1602.vhd" "" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 14 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 LCD1602 " "Info: Found entity 1: LCD1602" {  } { { "lcd1602.vhd" "" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "lcd1602 " "Info: Elaborating entity \"lcd1602\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "Clkk lcd1602.vhd(17) " "Info: (10035) Verilog HDL or VHDL information at lcd1602.vhd(17): object \"Clkk\" declared but not used" {  } { { "lcd1602.vhd" "" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 17 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Clk_Out lcd1602.vhd(35) " "Warning: VHDL Process Statement warning at lcd1602.vhd(35): signal \"Clk_Out\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "lcd1602.vhd" "" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 35 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "lcd1602.vhd(125) " "Info: VHDL Case Statement information at lcd1602.vhd(125): OTHERS choice is never selected" {  } { { "lcd1602.vhd" "" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 125 0 0 } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "Count\[0\]~0 21 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=21) from the following logic: \"Count\[0\]~0\"" {  } { { "lcd1602.vhd" "Count\[0\]~0" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 18 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|LCD1602\|Current_State 20 0 " "Info: State machine \"\|LCD1602\|Current_State\" contains 20 states and 0 state bits" {  } { { "lcd1602.vhd" "" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 16 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|LCD1602\|Current_State " "Info: Selected Auto state machine encoding method for state machine \"\|LCD1602\|Current_State\"" {  } { { "lcd1602.vhd" "" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 16 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|LCD1602\|Current_State " "Info: Encoding result for state machine \"\|LCD1602\|Current_State\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "5 " "Info: Completed encoding using 5 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Current_State~45 " "Info: Encoded state bit \"Current_State~45\"" {  } { { "lcd1602.vhd" "" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 16 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Current_State~44 " "Info: Encoded state bit \"Current_State~44\"" {  } { { "lcd1602.vhd" "" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 16 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Current_State~43 " "Info: Encoded state bit \"Current_State~43\"" {  } { { "lcd1602.vhd" "" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 16 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Current_State~42 " "Info: Encoded state bit \"Current_State~42\"" {  } { { "lcd1602.vhd" "" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 16 -1 0 } }  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "Current_State~41 " "Info: Encoded state bit \"Current_State~41\"" {  } { { "lcd1602.vhd" "" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 16 -1 0 } }  } 0}  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|LCD1602\|Current_State.set_dlnf 00000 " "Info: State \"\|LCD1602\|Current_State.set_dlnf\" uses code string \"00000\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|LCD1602\|Current_State.set_cursor 00001 " "Info: State \"\|LCD1602\|Current_State.set_cursor\" uses code string \"00001\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|LCD1602\|Current_State.set_dcb 00010 " "Info: State \"\|LCD1602\|Current_State.set_dcb\" uses code string \"00010\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|LCD1602\|Current_State.set_cgram 00011 " "Info: State \"\|LCD1602\|Current_State.set_cgram\" uses code string \"00011\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|LCD1602\|Current_State.write_cgram 01000 " "Info: State \"\|LCD1602\|Current_State.write_cgram\" uses code string \"01000\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|LCD1602\|Current_State.set_ddram 00100 " "Info: State \"\|LCD1602\|Current_State.set_ddram\" uses code string \"00100\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|LCD1602\|Current_State.writelcd1 00101 " "Info: State \"\|LCD1602\|Current_State.writelcd1\" uses code string \"00101\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|LCD1602\|Current_State.writelcd2 00110 " "Info: State \"\|LCD1602\|Current_State.writelcd2\" uses code string \"00110\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|LCD1602\|Current_State.writelcd3 00111 " "Info: State \"\|LCD1602\|Current_State.writelcd3\" uses code string \"00111\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|LCD1602\|Current_State.writelcd4 01010 " "Info: State \"\|LCD1602\|Current_State.writelcd4\" uses code string \"01010\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|LCD1602\|Current_State.writelcd5 01001 " "Info: State \"\|LCD1602\|Current_State.writelcd5\" uses code string \"01001\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|LCD1602\|Current_State.writelcd6 01100 " "Info: State \"\|LCD1602\|Current_State.writelcd6\" uses code string \"01100\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|LCD1602\|Current_State.writelcd7 01011 " "Info: State \"\|LCD1602\|Current_State.writelcd7\" uses code string \"01011\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|LCD1602\|Current_State.writelcd8 01110 " "Info: State \"\|LCD1602\|Current_State.writelcd8\" uses code string \"01110\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|LCD1602\|Current_State.writelcd9 01101 " "Info: State \"\|LCD1602\|Current_State.writelcd9\" uses code string \"01101\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|LCD1602\|Current_State.writelcd10 01111 " "Info: State \"\|LCD1602\|Current_State.writelcd10\" uses code string \"01111\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|LCD1602\|Current_State.writelcd11 10000 " "Info: State \"\|LCD1602\|Current_State.writelcd11\" uses code string \"10000\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|LCD1602\|Current_State.writelcd12 10001 " "Info: State \"\|LCD1602\|Current_State.writelcd12\" uses code string \"10001\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|LCD1602\|Current_State.writelcd13 10010 " "Info: State \"\|LCD1602\|Current_State.writelcd13\" uses code string \"10010\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|LCD1602\|Current_State.writelcd14 10011 " "Info: State \"\|LCD1602\|Current_State.writelcd14\" uses code string \"10011\"" {  } {  } 0}  } { { "lcd1602.vhd" "" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 16 -1 0 } }  } 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "\\control:cnt1\[0\] High " "Info: Power-up level of register \"\\control:cnt1\[0\]\" is not specified -- using power-up level of High to minimize register" {  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "\\control:cnt1\[0\] " "Warning: No clock transition on register \"\\control:cnt1\[0\]\" due to stuck clock or clock enable" {  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "\\control:cnt1\[0\] clock_enable VCC " "Warning: Reduced register \"\\control:cnt1\[0\]\" with stuck clock_enable port to stuck value VCC" {  } {  } 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "\\control:cnt1\[2\] High " "Info: Power-up level of register \"\\control:cnt1\[2\]\" is not specified -- using power-up level of High to minimize register" {  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "\\control:cnt1\[2\] " "Warning: No clock transition on register \"\\control:cnt1\[2\]\" due to stuck clock or clock enable" {  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "\\control:cnt1\[2\] clock_enable VCC " "Warning: Reduced register \"\\control:cnt1\[2\]\" with stuck clock_enable port to stuck value VCC" {  } {  } 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "\\control:cnt1\[1\] High " "Info: Power-up level of register \"\\control:cnt1\[1\]\" is not specified -- using power-up level of High to minimize register" {  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "\\control:cnt1\[1\] " "Warning: No clock transition on register \"\\control:cnt1\[1\]\" due to stuck clock or clock enable" {  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "\\control:cnt1\[1\] clock_enable VCC " "Warning: Reduced register \"\\control:cnt1\[1\]\" with stuck clock_enable port to stuck value VCC" {  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "LCD_RW GND " "Warning: Pin \"LCD_RW\" stuck at GND" {  } { { "lcd1602.vhd" "" { Text "C:/altera/quartus50/lcd1602/lcd1602.vhd" 9 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "Clk " "Info: Promoted clock signal driven by pin \"Clk\" to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "68 " "Info: Implemented 68 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "11 " "Info: Implemented 11 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "43 " "Info: Implemented 43 macrocells" {  } {  } 0} { "Info" "ISCL_SCL_TM_SEXPS" "12 " "Info: Implemented 12 shareable expanders" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 9 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 05 23:57:20 2007 " "Info: Processing ended: Thu Jul 05 23:57:20 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0}  } {  } 0}