lcd1602.tan.summary

来自「通过VERILOG HDL语言使用CPLD连接PS2键盘.」· SUMMARY 代码 · 共 57 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 5.000 ns
From           : Reset
To             : Clk_Out
From Clock     : 
To Clock       : Clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 13.100 ns
From           : LCD_Data[4]~reg0
To             : LCD_Data[4]
From Clock     : Clk
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 3.900 ns
From           : Reset
To             : LCD_Data[1]~reg0
From Clock     : 
To Clock       : Clk
Failed Paths   : 0

Type           : Clock Setup: 'Clk'
Slack          : N/A
Required Time  : None
Actual Time    : 70.92 MHz ( period = 14.100 ns )
From           : Current_State~43
To             : LCD_Data[3]~reg0
From Clock     : Clk
To Clock       : Clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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