boma.map.qmsg

通过VERILOG HDL语言使用CPLD连接PS2键盘.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 05 22:59:41 2007 " "Info: Processing started: Thu Jul 05 22:59:41 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off boma -c boma " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off boma -c boma" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "boma.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file boma.v" { { "Info" "ISGN_ENTITY_NAME" "1 boma " "Info: Found entity 1: boma" {  } { { "boma.v" "" { Text "C:/altera/quartus50/4switch/boma.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "boma " "Info: Elaborating entity \"boma\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "reset boma.v(8) " "Warning: Verilog HDL Always Construct warning at boma.v(8): variable \"reset\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "boma.v" "" { Text "C:/altera/quartus50/4switch/boma.v" 8 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 boma.v(10) " "Warning: Verilog HDL assignment warning at boma.v(10): truncated value with size 32 to match size of target (4)" {  } { { "boma.v" "" { Text "C:/altera/quartus50/4switch/boma.v" 10 0 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "13 " "Info: Implemented 13 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "4 " "Info: Implemented 4 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "4 " "Info: Implemented 4 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 05 22:59:43 2007 " "Info: Processing ended: Thu Jul 05 22:59:43 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}