boma.tan.qmsg

通过VERILOG HDL语言使用CPLD连接PS2键盘.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 05 22:59:50 2007 " "Info: Processing started: Thu Jul 05 22:59:50 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off boma -c boma " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off boma -c boma" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "reset b\[3\] 10.000 ns Longest " "Info: Longest tpd from source pin \"reset\" to destination pin \"b\[3\]\" is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns reset 1 PIN PIN_37 4 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_37; Fanout = 4; PIN Node = 'reset'" {  } { { "C:/altera/quartus50/4switch/db/boma_cmp.qrpt" "" { Report "C:/altera/quartus50/4switch/db/boma_cmp.qrpt" Compiler "boma" "UNKNOWN" "V1" "C:/altera/quartus50/4switch/db/boma.quartus_db" { Floorplan "C:/altera/quartus50/4switch/" "" "" { reset } "NODE_NAME" } "" } } { "boma.v" "" { Text "C:/altera/quartus50/4switch/boma.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(4.400 ns) 8.400 ns bb\[3\]~43 2 COMB LC33 1 " "Info: 2: + IC(2.600 ns) + CELL(4.400 ns) = 8.400 ns; Loc. = LC33; Fanout = 1; COMB Node = 'bb\[3\]~43'" {  } { { "C:/altera/quartus50/4switch/db/boma_cmp.qrpt" "" { Report "C:/altera/quartus50/4switch/db/boma_cmp.qrpt" Compiler "boma" "UNKNOWN" "V1" "C:/altera/quartus50/4switch/db/boma.quartus_db" { Floorplan "C:/altera/quartus50/4switch/" "" "7.000 ns" { reset bb[3]~43 } "NODE_NAME" } "" } } { "boma.v" "" { Text "C:/altera/quartus50/4switch/boma.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 10.000 ns b\[3\] 3 PIN PIN_25 0 " "Info: 3: + IC(0.000 ns) + CELL(1.600 ns) = 10.000 ns; Loc. = PIN_25; Fanout = 0; PIN Node = 'b\[3\]'" {  } { { "C:/altera/quartus50/4switch/db/boma_cmp.qrpt" "" { Report "C:/altera/quartus50/4switch/db/boma_cmp.qrpt" Compiler "boma" "UNKNOWN" "V1" "C:/altera/quartus50/4switch/db/boma.quartus_db" { Floorplan "C:/altera/quartus50/4switch/" "" "1.600 ns" { bb[3]~43 b[3] } "NODE_NAME" } "" } } { "boma.v" "" { Text "C:/altera/quartus50/4switch/boma.v" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.400 ns 74.00 % " "Info: Total cell delay = 7.400 ns ( 74.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns 26.00 % " "Info: Total interconnect delay = 2.600 ns ( 26.00 % )" {  } {  } 0}  } { { "C:/altera/quartus50/4switch/db/boma_cmp.qrpt" "" { Report "C:/altera/quartus50/4switch/db/boma_cmp.qrpt" Compiler "boma" "UNKNOWN" "V1" "C:/altera/quartus50/4switch/db/boma.quartus_db" { Floorplan "C:/altera/quartus50/4switch/" "" "10.000 ns" { reset bb[3]~43 b[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { reset reset~out bb[3]~43 b[3] } { 0.000ns 0.000ns 2.600ns 0.000ns } { 0.000ns 1.400ns 4.400ns 1.600ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 05 22:59:50 2007 " "Info: Processing ended: Thu Jul 05 22:59:50 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}