sysepic.h

MPC8560 for vxwork BSP

                                  EPIC_IN_DEST_REG_VECREGOFF)
#define EPIC_MSG_DEST_REG(irq)   (EPIC_MSG_VEC_REG(irq) + \
                                  EPIC_MSG_DEST_REG_VECREGOFF)

/* GCR register */

#define EPIC_GCR_RESET		BIT(31)
#define EPIC_GCR_MODE_MIXED	BIT(29)

/* IPI Vector/Priority registers */

#define EPIC_IPIVPR_INTR_MSK        BIT(31)
#define EPIC_IPIVPR_INTR_ACTIVE     BIT(30)
#define EPIC_IPIVPR_PRIORITY_MSK    (BIT(19) | BIT(18) | BIT(17) | BIT(16))
#define EPIC_IPIVPR_PRIORITY(p)     (((p) << 16) & EPIC_IPIVPR_PRIORITY_MSK)
#define EPIC_IPIVPR_VECTOR_MSK      (0xffff)
#define EPIC_IPIVPR_VECTOR(vec)     ((vec) & EPIC_IPIVPR_VECTOR_MSK)

/* Global Timer Vector/Priority registers */

#define EPIC_GTVPR_INTR_MSK        BIT(31)
#define EPIC_GTVPR_INTR_ACTIVE     BIT(30)
#define EPIC_GTVPR_PRIORITY_MSK    (BIT(19) | BIT(18) | BIT(17) | BIT(16))
#define EPIC_GTVPR_PRIORITY(p)     (((p) << 16) & EPIC_GTVPR_PRIORITY_MSK)
#define EPIC_GTVPR_VECTOR_MSK      (0xffff)
#define EPIC_GTVPR_VECTOR(vec)     ((vec) & EPIC_GTVPR_VECTOR_MSK)

/* Summary registers */

#define EPIC_IRQSR0_MSG_INT_MSK 0xf000
#define EPIC_IRQSR0_MSG_INT(n)  (BIT(15-(n)) & EPIC_IRQSR0_MSG_INT_MSK)
#define EPIC_IRQSR0_EX_INT_MSK  0xfff
#define EPIC_IRQSR0_EX_INT(n)   (BIT(11-(n)) & EPIC_IRQSR0_EX_INT_MSK)
#define EPIC_IRQSR1_IN_INT(n)   BIT(31-(n))
#define EPIC_CISR0_MSG_INT_MSK  0xf000
#define EPIC_CISR0_MSG_INT(n)   (BIT(15-(n)) & EPIC_CISR0_MSG_INT_MSK)
#define EPIC_CISR0_EX_INT_MSK   0xfff
#define EPIC_CISR0_EX_INT(n)    (BIT(11-(n)) & EPIC_CISR0_EX_INT_MSK)
#define EPIC_CISR1_IN_INT(n)    BIT(31-(n))

/* Message registers */

#define EPIC_MER_EN_MSK         0xf
#define EPIC_MER_EN(n)          (BIT(n) & EPIC_MER_EN_MSK)
#define EPIC_MSR_ST_MSK         0xf
#define EPIC_MSR_ST(n)          (BIT(n) & EPIC_MER_ST_MSK)

/* EIVPR registers */

#define EPIC_EIVPR_INTR_MSK         BIT(31)
#define EPIC_EIVPR_INTR_ACTIVE      BIT(30)
#define EPIC_EIVPR_INTR_POLARITY    BIT(23)
#define EPIC_EIVPR_INTR_SENSE       BIT(22)
#define EPIC_EIVPR_POLARITY(p)      ((p) << 23)
#define EPIC_EIVPR_SENS(s)          ((s) << 22)
#define EPIC_EIVPR_PRIORITY_MSK	    (BIT(19) | BIT(18) | BIT(17) | BIT(16))
#define EPIC_EIVPR_PRIORITY(p) 	    (((p) << 16) & EPIC_EIVPR_PRIORITY_MSK)
#define EPIC_EIVPR_VECTOR_MSK       (0xffff)
#define EPIC_EIVPR_VECTOR(vec) 	    ((vec) & EPIC_EIVPR_VECTOR_MSK)
#define EPIC_INT_ACT_LOW            0
#define EPIC_INT_ACT_HIGH           1
#define EPIC_INT_EDG_NEG            0
#define EPIC_INT_EDG_POS            1
#define EPIC_SENSE_LVL              1
#define EPIC_SENSE_EDG              0

/* EIDR registers */

#define EPIC_EIDR_EX_PIN        BIT(31)
#define EPIC_EIDR_CRIT_INT      BIT(30)

/* Options for *VPR and *IDR registers */

#define EPIC_OPT_EN_MSK             EPIC_EIVPR_INTR_MSK
#define EPIC_OPT_EN_Y               0x00000000
#define EPIC_OPT_EN_N               0x10000000
#define EPIC_OPT_POLAR_MSK          EPIC_EIVPR_INTR_POLARITY
#define EPIC_OPT_POLAR_ACT_LOW      0x00000000
#define EPIC_OPT_POLAR_ACT_HIGH     0x00800000
#define EPIC_OPT_POLAR_EDG_NEG      0x00000000
#define EPIC_OPT_POLAR_EDG_POS      0x00800000
#define EPIC_OPT_SENSE_MSK          EPIC_EIVPR_INTR_SENSE
#define EPIC_OPT_SENSE_EDG          0x00000000
#define EPIC_OPT_SENSE_LVL          0x00400000
#define EPIC_OPT_PRI_MSK            EPIC_EIVPR_PRIORITY_MSK
#define EPIC_OPT_PRI_VALUE(p)       EPIC_EIVPR_PRIORITY(p)
#define EPIC_OPT_EXPIN_MSK          (EPIC_EIDR_EX_PIN >> 16)
#define EPIC_OPT_EXPIN_OFF          (0x00000000 >> 16)
#define EPIC_OPT_EXPIN_ON           (0x80000000 >> 16)
#define EPIC_OPT_CRIT_MSK           (EPIC_EIDR_CRIT_INT >> 16)
#define EPIC_OPT_CRIT_OFF           (0x00000000 >> 16)
#define EPIC_OPT_CRIT_ON            (0x40000000 >> 16)

/* IIVPR registers */

#define EPIC_IIVPR_INTR_MSK         BIT(31)
#define EPIC_IIVPR_INTR_ACTIVE      BIT(30)
#define EPIC_IIVPR_INTR_POLARITY    BIT(23)
#define EPIC_IIVPR_POLARITY(p)      ((p) << 23)
#define EPIC_IIVPR_PRIORITY_MSK     (BIT(19) | BIT(18) | BIT(17) | BIT(16))
#define EPIC_IIVPR_PRIORITY(p)      (((p) << 16) & EPIC_IIVPR_PRIORITY_MSK)
#define EPIC_IIVPR_VECTOR_MSK       (0xffff)
#define EPIC_IIVPR_VECTOR(vec)      ((vec) & EPIC_IIVPR_VECTOR_MSK)

/* IIDR registers */

#define EPIC_IIDR_EX_PIN        BIT(31)
#define EPIC_IIDR_CRIT_INT      BIT(30)

/* MIVPR registers */

#define EPIC_MIVPR_INTR_MSK         BIT(31)
#define EPIC_MIVPR_INTR_ACTIVE      BIT(30)
#define EPIC_MIVPR_PRIORITY_MSK     (BIT(19) | BIT(18) | BIT(17) | BIT(16))
#define EPIC_MIVPR_PRIORITY(p)      (((p) << 16) & EPIC_MIVPR_PRIORITY_MSK)
#define EPIC_MIVPR_VECTOR_MSK       (0xffff)
#define EPIC_MIVPR_VECTOR(vec)      ((vec) & EPIC_MIVPR_VECTOR_MSK)

/* MIDR registers */

#define EPIC_MIDR_EX_PIN        BIT(31)
#define EPIC_MIDR_CRIT_INT      BIT(30)

/* IPIDR registers */

#define EPIC_IPIDR_P0           BIT(0)

/* CTPR register */

#define EPIC_CTPR_TASKPRI_MSK   (BIT(3) | BIT(2) | BIT(1) | BIT(0))
#define EPIC_CTPR_TASKPRI(p)    ((p) & EPIC_CTPR_TASKPRI_MSK)

/* WHOAMI register */

#define EPIC_WHOAMI_ID_MSK      (BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0))
#define EPIC_WHOAMI_ID(n)       ((n) & EPIC_WHOAMI_ID_MSK)


#define EPIC_INTER_IN_SERVICE	 2

#define EPIC_IN_INTERRUPT 	20	/* internal type */
#define EPIC_EX_INTERRUPT 	21	/* external type */
#define EPIC_INV_INTER_SOURCE 	22	/* invalid interrupt source */
#define EPIC_GT_INTERRUPT 	23	/* global timer type */
#define EPIC_MSG_INTERRUPT 	24	/* message type */
#define EPIC_IPI_INTERRUPT 	25	/* inter-processor type */
#define EPIC_VEC_HAS_NO_IDR     26	/* vector has no IDR reg */
#define EPIC_VEC_OPTION_NA      27	/* option(s) not avail for this vec */
#define EPIC_VEC_OPTION_INV     28	/* option mask is invalid */

#define EPIC_MAX_EXT_IRQS	12
#define EPIC_MAX_IN_IRQS	32
#define EPIC_MAX_GT_IRQS	4
#define EPIC_MAX_MSG_IRQS	4
#define EPIC_MAX_IPI_IRQS	4

#define EPIC_VEC_EXT_IRQ0       0
#define EPIC_VEC_IN_IRQ0        (EPIC_VEC_EXT_IRQ0 + EPIC_MAX_EXT_IRQS)
#define EPIC_VEC_GT_IRQ0        (EPIC_VEC_IN_IRQ0 + EPIC_MAX_IN_IRQS)
#define EPIC_VEC_MSG_IRQ0       (EPIC_VEC_GT_IRQ0 + EPIC_MAX_GT_IRQS)
#define EPIC_VEC_IPI_IRQ0       (EPIC_VEC_MSG_IRQ0 + EPIC_MAX_MSG_IRQS)
#define EPIC_VEC_CTRL_EXT       (EPIC_VEC_IPI_IRQ0 + EPIC_MAX_IPI_IRQS)
#define EPIC_MAX_ALL_IRQS       EPIC_VEC_CTRL_EXT

#define EPIC_PRIORITY_MIN	0    /* minimum level of priority */
#define EPIC_PRIORITY_MAX	15   /* maximum level of priority */
#define EPIC_PRIORITY_DEFAULT	3
#define EPIC_INV_PRIO_ERROR	((ULONG)(-1))

#define EPIC_L2CACHE_INT_NUM        0
#define EPIC_L2CACHE_INT_VEC        (EPIC_L2CACHE_INT_NUM + EPIC_VEC_IN_IRQ0)
#define EPIC_ECM_INT_NUM            1
#define EPIC_ECM_INT_VEC            (EPIC_ECM_INT_NUM + EPIC_VEC_IN_IRQ0)
#define EPIC_DDR_INT_NUM            2
#define EPIC_DDR_INT_VEC            (EPIC_DDR_INT_NUM + EPIC_VEC_IN_IRQ0)
#define EPIC_LBC_INT_NUM            3
#define EPIC_LBC_INT_VEC            (EPIC_LBC_INT_NUM + EPIC_VEC_IN_IRQ0)
#define EPIC_DMA0_INT_NUM           4
#define EPIC_DMA0_INT_VEC           (EPIC_DMA0_INT_NUM + EPIC_VEC_IN_IRQ0)
#define EPIC_DMA1_INT_NUM           5
#define EPIC_DMA1_INT_VEC           (EPIC_DMA1_INT_NUM + EPIC_VEC_IN_IRQ0)
#define EPIC_DMA2_INT_NUM           6
#define EPIC_DMA2_INT_VEC           (EPIC_DMA2_INT_NUM + EPIC_VEC_IN_IRQ0)
#define EPIC_DMA3_INT_NUM           7
#define EPIC_DMA3_INT_VEC           (EPIC_DMA3_INT_NUM + EPIC_VEC_IN_IRQ0)
#define EPIC_PCI_INT_NUM            8
#define EPIC_PCI_INT_VEC            (EPIC_PCI_INT_NUM + EPIC_VEC_IN_IRQ0)
#define EPIC_RIOWRERR_INT_NUM       9
#define EPIC_RIOWRERR_INT_VEC       (EPIC_RIOWRERR_INT_NUM + EPIC_VEC_IN_IRQ0)
#define EPIC_RIODBELL_INT_NUM       10
#define EPIC_RIODBELL_INT_VEC       (EPIC_RIODBELL_INT_NUM + EPIC_VEC_IN_IRQ0)
#define EPIC_RIOMSGOUT_INT_NUM      11
#define EPIC_RIOMSGOUT_INT_VEC      (EPIC_RIOMSGOUT_INT_NUM + EPIC_VEC_IN_IRQ0)
#define EPIC_RIOMSGIN_INT_NUM       12
#define EPIC_RIOMSGIN_INT_VEC       (EPIC_RIOMSGIN_INT_NUM + EPIC_VEC_IN_IRQ0)
#define EPIC_TSEC1TX_INT_NUM        13
#define EPIC_TSEC1TX_INT_VEC        (EPIC_TSEC1TX_INT_NUM + EPIC_VEC_IN_IRQ0)
#define EPIC_TSEC1RX_INT_NUM        14
#define EPIC_TSEC1RX_INT_VEC        (EPIC_TSEC1RX_INT_NUM + EPIC_VEC_IN_IRQ0)
#define EPIC_RESV15_INT_NUM         15
#define EPIC_RESV15_INT_VEC         (EPIC_RESV15_INT_NUM + EPIC_VEC_IN_IRQ0)
#define EPIC_RESV16_INT_NUM         16
#define EPIC_RESV16_INT_VEC         (EPIC_RESV16_INT_NUM + EPIC_VEC_IN_IRQ0)
#define EPIC_RESV17_INT_NUM         17
#define EPIC_RESV17_INT_VEC         (EPIC_RESV17_INT_NUM + EPIC_VEC_IN_IRQ0)
#define EPIC_TSEC1ERR_INT_NUM       18
#define EPIC_TSEC1ERR_INT_VEC       (EPIC_TSEC1ERR_INT_NUM + EPIC_VEC_IN_IRQ0)
#define EPIC_TSEC2TX_INT_NUM        19
#define EPIC_TSEC2TX_INT_VEC        (EPIC_TSEC2TX_INT_NUM + EPIC_VEC_IN_IRQ0)
#define EPIC_TSEC2RX_INT_NUM        20
#define EPIC_TSEC2RX_INT_VEC        (EPIC_TSEC2RX_INT_NUM + EPIC_VEC_IN_IRQ0)
#define EPIC_RESV21_INT_NUM         21
#define EPIC_RESV21_INT_VEC         (EPIC_RESV21_INT_NUM + EPIC_VEC_IN_IRQ0)
#define EPIC_RESV22_INT_NUM         22
#define EPIC_RESV22_INT_VEC         (EPIC_RESV22_INT_NUM + EPIC_VEC_IN_IRQ0)
#define EPIC_RESV23_INT_NUM         23
#define EPIC_RESV23_INT_VEC         (EPIC_RESV23_INT_NUM + EPIC_VEC_IN_IRQ0)
#define EPIC_TSEC2ERR_INT_NUM       24
#define EPIC_TSEC2ERR_INT_VEC       (EPIC_TSEC2ERR_INT_NUM + EPIC_VEC_IN_IRQ0)
#define EPIC_FEC_INT_NUM            25
#define EPIC_FEC_INT_VEC            (EPIC_FEC_INT_NUM + EPIC_VEC_IN_IRQ0)
#define EPIC_DUART_INT_NUM          26
#define EPIC_DUART_INT_VEC          (EPIC_DUART_INT_NUM + EPIC_VEC_IN_IRQ0)
#define EPIC_I2C_INT_NUM            27
#define EPIC_I2C_INT_VEC            (EPIC_I2C_INT_NUM + EPIC_VEC_IN_IRQ0)
#define EPIC_PERFMON_INT_NUM        28
#define EPIC_PERFMON_INT_VEC        (EPIC_PERFMON_INT_NUM + EPIC_VEC_IN_IRQ0)
#define EPIC_IIN29_INT_NUM          29
#define EPIC_IIN29_INT_VEC          (EPIC_IIN29_INT_NUM + EPIC_VEC_IN_IRQ0)
#define EPIC_CPM_INT_NUM            30
#define EPIC_CPM_INT_VEC            (EPIC_CPM_INT_NUM + EPIC_VEC_IN_IRQ0)
#define EPIC_IIN31_INT_NUM          31
#define EPIC_IIN31_INT_VEC          (EPIC_IIN31_INT_NUM + EPIC_VEC_IN_IRQ0)


IMPORT STATUS	sysEpicIntConnect (VOIDFUNCPTR * vector, VOIDFUNCPTR routine,
                                   int parameter);
IMPORT int	sysEpicIntEnable (int vector);
IMPORT int	sysEpicIntDisable (int vector);
IMPORT void   	sysEpicInit (void);
IMPORT STATUS 	sysEpicIntrInit (void);
IMPORT int	sysEpicVecOptionsSet (int vector, UINT32 mask, UINT32 options);
IMPORT UINT32	sysEpicVecOptionsGet (int vector);
#ifdef INCLUDE_EPIC_CRT_INTR
IMPORT UINT32	epicCisr0Get (void);
IMPORT UINT32	epicCisr1Get (void);
IMPORT int	sysEpicCrtIntSet (int vector);
IMPORT int	sysEpicCrtIntUnset (int vector);
IMPORT int	sysEpicCrtIntGet (int vector);
#endif  /* INCLUDE_EPIC_CRT_INTR */
IMPORT int  	epicCurTaskPrioSet (int prioNum);
IMPORT int    	epicIntAck (void);
IMPORT void   	epicEOI (void);
IMPORT ULONG	epicGetVecRegAdrs (int vector);
IMPORT ULONG	epicGetDestRegAdrs (int vector);
IMPORT STATUS 	epicIntSourceSet (ULONG srcAddr, int polarity,
                                  int sense, int priority, int vector);
IMPORT STATUS 	epicIntSourceGet (ULONG srcAddr, int * pEnableMask,
                                  int * pPolarity, int * pSense,
                                  int * pPriority, int * pVector);
IMPORT UINT32	sysEpicRegRead (ULONG regNum);
IMPORT void	sysEpicRegWrite (ULONG regNum, UINT32 regVal);

#ifdef __cplusplus
}
#endif

#endif	/* __INCsysEpich */