sysepic.h

MPC8560 for vxwork BSP

/* sysEpic.h - Embedded Programmable Interrupt Controller (EPIC) driver */

/* Copyright 1984-2003 Wind River Systems, Inc. */
/* Copyright 1996, 1998 Motorola, Inc. */

/*
modification history
--------------------
01f,06may04,mil  Fixed macro INCLUDE_EPIC_CRT_INTR.
01e,13oct03,mil  Added options for polarity and sense.
01d,29jul03,dtr  Set EUMBARVAL to CCSBAR.
01c,08jan03,mil  Created based on Sandpoint MPC107.
*/

#ifndef	__INCsysEpich
#define	__INCsysEpich

#ifdef __cplusplus
extern "C" {
#endif

/*  interrupt handler description  */
    
typedef struct intHandlerDesc     
    {
    VOIDFUNCPTR			vec;	/* interrupt vector */
    int				arg;	/* interrupt handler argument */
    struct  intHandlerDesc *	next;	/* pointer to the next handler */
    } INT_HANDLER_DESC;

/*   limit values  */

/* bits 31(MSB)...0(LSB) enable only 1 bit at bit x */
#define BIT(x)          (1 << (x))

/* bits 31(MSB)...0(LSB) enable from bit x to bit y where y>x */
#define BITS_M2N(x, y)  (( 1 << ((y)-(x)+1) ) - 1) << (x)

/* bits 31(MSB)...0(LSB) from bit x towards LSB enable y bits */          
#define BITS(x, y)      BITS_M2N(x-y+1, x)

#define  INTERRUPT_TABLESIZE   256
    
#define EPIC_CCSROFF  		0x40000			/* EUMBBAR of EPIC  */

/* default is LEVEL sensitive, ACTIVE_HIGH polarity */

#ifndef EPIC_EX_DFT_SENSE
#   define EPIC_EX_DFT_SENSE	EPIC_SENSE_LVL
#endif  /* EPIC_EX_DFT_SENSE */

#ifndef EPIC_EX_DFT_POLAR
#   define EPIC_EX_DFT_POLAR	EPIC_INT_ACT_HIGH
#endif  /* EPIC_EX_DFT_POLAR */

#ifndef EPIC_IN_DFT_POLAR
#   define EPIC_IN_DFT_POLAR	EPIC_INT_ACT_HIGH
#endif  /* EPIC_IN_DFT_POLAR */

/*   Private Access Registers  */
#define EPIC_IPI_DPATCH_REG0	(EPIC_CCSROFF + 0x00040)/* IPI0 dispatch */
#define EPIC_IPI_DPATCH_REG1	(EPIC_CCSROFF + 0x00050)/* IPI1 dispatch */
#define EPIC_IPI_DPATCH_REG2	(EPIC_CCSROFF + 0x00060)/* IPI2 dispatch */
#define EPIC_IPI_DPATCH_REG3	(EPIC_CCSROFF + 0x00070)/* IPI3 dispatch */
#define EPIC_CTASK_PRI_REG	(EPIC_CCSROFF + 0x00080)/* Cur Task Prio */
#define EPIC_WHO_AM_I_REG	(EPIC_CCSROFF + 0x00090)/* Who am I */
#define EPIC_INT_ACK_REG	(EPIC_CCSROFF + 0x000a0)/* Int ack */
#define EPIC_EOI_REG		(EPIC_CCSROFF + 0x000b0)/* End of Int */

/*   Global and Timer  */
#define EPIC_FEATURES_REG	(EPIC_CCSROFF + 0x01000)/* Feature reporting */
#define EPIC_GLOBAL_REG		(EPIC_CCSROFF + 0x01020)/* Global config.  */
#define EPIC_VENDOR_ID_REG	(EPIC_CCSROFF + 0x01080)/* Vendor id */
#define EPIC_PROC_INIT_REG	(EPIC_CCSROFF + 0x01090)/* Processor init. */
#define EPIC_IPI_0_VEC_REG	(EPIC_CCSROFF + 0x010a0)/* IPI0 vect/prio */
#define EPIC_IPI_1_VEC_REG	(EPIC_CCSROFF + 0x010b0)/* IPI1 vect/prio */
#define EPIC_IPI_2_VEC_REG	(EPIC_CCSROFF + 0x010c0)/* IPI2 vect/prio */
#define EPIC_IPI_3_VEC_REG	(EPIC_CCSROFF + 0x010d0)/* IPI3 vect/prio */
#define EPIC_SPUR_VEC_REG	(EPIC_CCSROFF + 0x010e0)/* Spurious vector */
#define EPIC_TM_FREQ_REG	(EPIC_CCSROFF + 0x010f0)/* Timer Frequency */

#define EPIC_TM0_CUR_COUNT_REG	(EPIC_CCSROFF + 0x01100)/* Gbl TM0 Cur. Count*/
#define EPIC_TM0_BASE_COUNT_REG	(EPIC_CCSROFF + 0x01110)/* Gbl TM0 Base Count*/
#define EPIC_TM0_VEC_REG	(EPIC_CCSROFF + 0x01120)/* Gbl TM0 Vector Pri*/
#define EPIC_TM0_DES_REG	(EPIC_CCSROFF + 0x01130)/* Gbl TM0 Dest. */

#define EPIC_TM1_CUR_COUNT_REG	(EPIC_CCSROFF + 0x01140)/* Gbl TM1 Cur. Count*/
#define EPIC_TM1_BASE_COUNT_REG	(EPIC_CCSROFF + 0x01150)/* Gbl TM1 Base Count*/
#define EPIC_TM1_VEC_REG	(EPIC_CCSROFF + 0x01160)/* Gbl TM1 Vector Pri*/
#define EPIC_TM1_DES_REG	(EPIC_CCSROFF + 0x01170)/* Gbl TM1 Dest. */

#define EPIC_TM2_CUR_COUNT_REG	(EPIC_CCSROFF + 0x01180)/* Gbl TM2 Cur. Count*/
#define EPIC_TM2_BASE_COUNT_REG	(EPIC_CCSROFF + 0x01190)/* Gbl TM2 Base Count*/
#define EPIC_TM2_VEC_REG	(EPIC_CCSROFF + 0x011a0)/* Gbl TM2 Vector Pri*/
#define EPIC_TM2_DES_REG	(EPIC_CCSROFF + 0x011b0)/* Gbl TM2 Dest */

#define EPIC_TM3_CUR_COUNT_REG	(EPIC_CCSROFF + 0x011c0)/* Gbl TM3 Cur. Count*/
#define EPIC_TM3_BASE_COUNT_REG	(EPIC_CCSROFF + 0x011d0)/* Gbl TM3 Base Count*/
#define EPIC_TM3_VEC_REG	(EPIC_CCSROFF + 0x011e0)/* Gbl TM3 Vector Pri*/
#define EPIC_TM3_DES_REG	(EPIC_CCSROFF + 0x011f0)/* Gbl TM3 Dest. */

#define EPIC_TM_CTRL		(EPIC_CCSROFF + 0x01300)/* Timer Control */
#define EPIC_IRQ_SUMM_REG0	(EPIC_CCSROFF + 0x01310)/* IRQ_OUT Summary 0 */
#define EPIC_IRQ_SUMM_REG1	(EPIC_CCSROFF + 0x01320)/* IRQ_OUT Summary 1 */
#define EPIC_CRIT_SUMM_REG0	(EPIC_CCSROFF + 0x01330)/* Crit Int Summary 0 */
#define EPIC_CRIT_SUMM_REG1	(EPIC_CCSROFF + 0x01340)/* Crit Int Summary 1 */
#define EPIC_PERFMON_0_MSK_REG0	(EPIC_CCSROFF + 0x01350)/* PerfMon 0 Mask 0 */
#define EPIC_PERFMON_0_MSK_REG1	(EPIC_CCSROFF + 0x01360)/* PerfMon 0 Mask 1 */
#define EPIC_PERFMON_1_MSK_REG0	(EPIC_CCSROFF + 0x01370)/* PerfMon 1 Mask 0 */
#define EPIC_PERFMON_1_MSK_REG1	(EPIC_CCSROFF + 0x01380)/* PerfMon 1 Mask 1 */
#define EPIC_PERFMON_2_MSK_REG0	(EPIC_CCSROFF + 0x01390)/* PerfMon 2 Mask 0 */
#define EPIC_PERFMON_2_MSK_REG1	(EPIC_CCSROFF + 0x013a0)/* PerfMon 2 Mask 1 */
#define EPIC_PERFMON_3_MSK_REG0	(EPIC_CCSROFF + 0x013b0)/* PerfMon 3 Mask 0 */
#define EPIC_PERFMON_3_MSK_REG1	(EPIC_CCSROFF + 0x013c0)/* PerfMon 3 Mask 1 */
#define EPIC_MSG_REG0		(EPIC_CCSROFF + 0x01400)/* Message 0 */
#define EPIC_MSG_REG1		(EPIC_CCSROFF + 0x01410)/* Message 1 */
#define EPIC_MSG_REG2		(EPIC_CCSROFF + 0x01420)/* Message 2 */
#define EPIC_MSG_REG3		(EPIC_CCSROFF + 0x01430)/* Message 3 */
#define EPIC_MSG_EN_REG		(EPIC_CCSROFF + 0x01500)/* Message Enable */
#define EPIC_MSG_STATE_REG	(EPIC_CCSROFF + 0x01510)/* Message Status */

/*   Interrupt Source Config  */
#define EPIC_EX_INT0_VEC_REG	(EPIC_CCSROFF + 0x10000)/* Ext IRQ0 vect/prio*/
#define EPIC_EX_INT0_DES_REG	(EPIC_CCSROFF + 0x10010)/* Ext IRQ0 Dest */
#define EPIC_EX_INT1_VEC_REG	(EPIC_CCSROFF + 0x10020)/* Ext IRQ1 vect/prio*/
#define EPIC_EX_INT1_DES_REG	(EPIC_CCSROFF + 0x10030)/* Ext IRQ1 Dest */
#define EPIC_EX_INT2_VEC_REG	(EPIC_CCSROFF + 0x10040)/* Ext IRQ2 vect/prio*/
#define EPIC_EX_INT2_DES_REG	(EPIC_CCSROFF + 0x10050)/* Ext IRQ2 Dest */
#define EPIC_EX_INT3_VEC_REG	(EPIC_CCSROFF + 0x10060)/* Ext IRQ3 vect/prio*/
#define EPIC_EX_INT3_DES_REG	(EPIC_CCSROFF + 0x10070)/* Ext IRQ3 Dest */
#define EPIC_EX_INT4_VEC_REG	(EPIC_CCSROFF + 0x10080)/* Ext IRQ4 vect/prio*/
#define EPIC_EX_INT4_DES_REG	(EPIC_CCSROFF + 0x10090)/* Ext IRQ4 Dest */
#define EPIC_EX_INT5_VEC_REG	(EPIC_CCSROFF + 0x100a0)/* Ext IRQ5 vect/prio*/
#define EPIC_EX_INT5_DES_REG	(EPIC_CCSROFF + 0x100b0)/* Ext IRQ5 Dest */
#define EPIC_EX_INT6_VEC_REG	(EPIC_CCSROFF + 0x100c0)/* Ext IRQ6 vect/prio*/
#define EPIC_EX_INT6_DES_REG	(EPIC_CCSROFF + 0x100d0)/* Ext IRQ6 Dest */
#define EPIC_EX_INT7_VEC_REG	(EPIC_CCSROFF + 0x100e0)/* Ext IRQ7 vect/prio*/
#define EPIC_EX_INT7_DES_REG	(EPIC_CCSROFF + 0x100f0)/* Ext IRQ7 Dest */
#define EPIC_EX_INT8_VEC_REG	(EPIC_CCSROFF + 0x10100)/* Ext IRQ8 vect/prio*/
#define EPIC_EX_INT8_DES_REG	(EPIC_CCSROFF + 0x10110)/* Ext IRQ8 Dest */
#define EPIC_EX_INT9_VEC_REG	(EPIC_CCSROFF + 0x10120)/* Ext IRQ9 vect/prio*/
#define EPIC_EX_INT9_DES_REG	(EPIC_CCSROFF + 0x10130)/* Ext IRQ9 Dest */
#define EPIC_EX_INT10_VEC_REG	(EPIC_CCSROFF + 0x10140)/* Ext IRQ10 vect/pri*/
#define EPIC_EX_INT10_DES_REG	(EPIC_CCSROFF + 0x10150)/* Ext IRQ10 Dest */
#define EPIC_EX_INT11_VEC_REG	(EPIC_CCSROFF + 0x10160)/* Ext IRQ11 vect/pri*/
#define EPIC_EX_INT11_DES_REG	(EPIC_CCSROFF + 0x10170)/* Ext IRQ11 Dest */

#define EPIC_IN_INT0_VEC_REG	(EPIC_CCSROFF + 0x10200)/* Int IRQ0 vect/prio*/
#define EPIC_IN_INT0_DES_REG	(EPIC_CCSROFF + 0x10210)/* Int IRQ0 Dest */
#define EPIC_IN_INT1_VEC_REG	(EPIC_CCSROFF + 0x10220)/* Int IRQ1 vect/prio*/
#define EPIC_IN_INT1_DES_REG	(EPIC_CCSROFF + 0x10230)/* Int IRQ1 Dest */
#define EPIC_IN_INT2_VEC_REG	(EPIC_CCSROFF + 0x10240)/* Int IRQ2 vect/prio*/
#define EPIC_IN_INT2_DES_REG	(EPIC_CCSROFF + 0x10250)/* Int IRQ2 Dest */
#define EPIC_IN_INT3_VEC_REG	(EPIC_CCSROFF + 0x10260)/* Int IRQ3 vect/prio*/
#define EPIC_IN_INT3_DES_REG	(EPIC_CCSROFF + 0x10270)/* Int IRQ3 Dest */
#define EPIC_IN_INT4_VEC_REG	(EPIC_CCSROFF + 0x10280)/* Int IRQ4 vect/prio*/
#define EPIC_IN_INT4_DES_REG	(EPIC_CCSROFF + 0x10290)/* Int IRQ4 Dest */
#define EPIC_IN_INT5_VEC_REG	(EPIC_CCSROFF + 0x102a0)/* Int IRQ5 vect/prio*/
#define EPIC_IN_INT5_DES_REG	(EPIC_CCSROFF + 0x102b0)/* Int IRQ5 Dest */
#define EPIC_IN_INT6_VEC_REG	(EPIC_CCSROFF + 0x102c0)/* Int IRQ6 vect/prio*/
#define EPIC_IN_INT6_DES_REG	(EPIC_CCSROFF + 0x102d0)/* Int IRQ6 Dest */
#define EPIC_IN_INT7_VEC_REG	(EPIC_CCSROFF + 0x102e0)/* Int IRQ7 vect/prio*/
#define EPIC_IN_INT7_DES_REG	(EPIC_CCSROFF + 0x102f0)/* Int IRQ7 Dest */
#define EPIC_IN_INT8_VEC_REG	(EPIC_CCSROFF + 0x10300)/* Int IRQ8 vect/prio*/
#define EPIC_IN_INT8_DES_REG	(EPIC_CCSROFF + 0x10310)/* Int IRQ8 Dest */
#define EPIC_IN_INT9_VEC_REG	(EPIC_CCSROFF + 0x10320)/* Int IRQ9 vect/prio*/
#define EPIC_IN_INT9_DES_REG	(EPIC_CCSROFF + 0x10330)/* Int IRQ9 Dest */
#define EPIC_IN_INT10_VEC_REG	(EPIC_CCSROFF + 0x10340)/* Int IRQ10 vect/pri*/
#define EPIC_IN_INT10_DES_REG	(EPIC_CCSROFF + 0x10350)/* Int IRQ10 Dest */
#define EPIC_IN_INT11_VEC_REG	(EPIC_CCSROFF + 0x10360)/* Int IRQ11 vect/pri*/
#define EPIC_IN_INT11_DES_REG	(EPIC_CCSROFF + 0x10370)/* Int IRQ11 Dest */
#define EPIC_IN_INT12_VEC_REG	(EPIC_CCSROFF + 0x10380)/* Int IRQ12 vect/pri*/
#define EPIC_IN_INT12_DES_REG	(EPIC_CCSROFF + 0x10390)/* Int IRQ12 Dest */
#define EPIC_IN_INT13_VEC_REG	(EPIC_CCSROFF + 0x103a0)/* Int IRQ13 vect/pri*/
#define EPIC_IN_INT13_DES_REG	(EPIC_CCSROFF + 0x103b0)/* Int IRQ13 Dest */
#define EPIC_IN_INT14_VEC_REG	(EPIC_CCSROFF + 0x103c0)/* Int IRQ14 vect/pri*/
#define EPIC_IN_INT14_DES_REG	(EPIC_CCSROFF + 0x103d0)/* Int IRQ14 Dest */
#define EPIC_IN_INT15_VEC_REG	(EPIC_CCSROFF + 0x103e0)/* Int IRQ15 vect/pri*/
#define EPIC_IN_INT15_DES_REG	(EPIC_CCSROFF + 0x103f0)/* Int IRQ15 Dest */
#define EPIC_IN_INT16_VEC_REG	(EPIC_CCSROFF + 0x10400)/* Int IRQ16 vect/pri*/
#define EPIC_IN_INT16_DES_REG	(EPIC_CCSROFF + 0x10410)/* Int IRQ16 Dest */
#define EPIC_IN_INT17_VEC_REG	(EPIC_CCSROFF + 0x10420)/* Int IRQ17 vect/pri*/
#define EPIC_IN_INT17_DES_REG	(EPIC_CCSROFF + 0x10430)/* Int IRQ17 Dest */
#define EPIC_IN_INT18_VEC_REG	(EPIC_CCSROFF + 0x10440)/* Int IRQ18 vect/pri*/
#define EPIC_IN_INT18_DES_REG	(EPIC_CCSROFF + 0x10450)/* Int IRQ18 Dest */
#define EPIC_IN_INT19_VEC_REG	(EPIC_CCSROFF + 0x10460)/* Int IRQ19 vect/pri*/
#define EPIC_IN_INT19_DES_REG	(EPIC_CCSROFF + 0x10470)/* Int IRQ19 Dest */
#define EPIC_IN_INT20_VEC_REG	(EPIC_CCSROFF + 0x10480)/* Int IRQ20 vect/pri*/
#define EPIC_IN_INT20_DES_REG	(EPIC_CCSROFF + 0x10490)/* Int IRQ20 Dest */
#define EPIC_IN_INT21_VEC_REG	(EPIC_CCSROFF + 0x104a0)/* Int IRQ21 vect/pri*/
#define EPIC_IN_INT21_DES_REG	(EPIC_CCSROFF + 0x104b0)/* Int IRQ21 Dest */
#define EPIC_IN_INT22_VEC_REG	(EPIC_CCSROFF + 0x104c0)/* Int IRQ22 vect/pri*/
#define EPIC_IN_INT22_DES_REG	(EPIC_CCSROFF + 0x104d0)/* Int IRQ22 Dest */
#define EPIC_IN_INT23_VEC_REG	(EPIC_CCSROFF + 0x104e0)/* Int IRQ23 vect/pri*/
#define EPIC_IN_INT23_DES_REG	(EPIC_CCSROFF + 0x104f0)/* Int IRQ23 Dest */
#define EPIC_IN_INT24_VEC_REG	(EPIC_CCSROFF + 0x10500)/* Int IRQ24 vect/pri*/
#define EPIC_IN_INT24_DES_REG	(EPIC_CCSROFF + 0x10510)/* Int IRQ24 Dest */
#define EPIC_IN_INT25_VEC_REG	(EPIC_CCSROFF + 0x10520)/* Int IRQ25 vect/pri*/
#define EPIC_IN_INT25_DES_REG	(EPIC_CCSROFF + 0x10530)/* Int IRQ25 Dest */
#define EPIC_IN_INT26_VEC_REG	(EPIC_CCSROFF + 0x10540)/* Int IRQ26 vect/pri*/
#define EPIC_IN_INT26_DES_REG	(EPIC_CCSROFF + 0x10550)/* Int IRQ26 Dest */
#define EPIC_IN_INT27_VEC_REG	(EPIC_CCSROFF + 0x10560)/* Int IRQ27 vect/pri*/
#define EPIC_IN_INT27_DES_REG	(EPIC_CCSROFF + 0x10570)/* Int IRQ27 Dest */
#define EPIC_IN_INT28_VEC_REG	(EPIC_CCSROFF + 0x10580)/* Int IRQ28 vect/pri*/
#define EPIC_IN_INT28_DES_REG	(EPIC_CCSROFF + 0x10590)/* Int IRQ28 Dest */
#define EPIC_IN_INT29_VEC_REG	(EPIC_CCSROFF + 0x105a0)/* Int IRQ29 vect/pri*/
#define EPIC_IN_INT29_DES_REG	(EPIC_CCSROFF + 0x105b0)/* Int IRQ29 Dest */
#define EPIC_IN_INT30_VEC_REG	(EPIC_CCSROFF + 0x105c0)/* Int IRQ30 vect/pri*/
#define EPIC_IN_INT30_DES_REG	(EPIC_CCSROFF + 0x105d0)/* Int IRQ30 Dest */
#define EPIC_IN_INT31_VEC_REG	(EPIC_CCSROFF + 0x105e0)/* Int IRQ31 vect/pri*/
#define EPIC_IN_INT31_DES_REG	(EPIC_CCSROFF + 0x105f0)/* Int IRQ31 Dest */

#define EPIC_MSG_INT0_VEC_REG	(EPIC_CCSROFF + 0x11600)/* MSG INT0 vect/prio*/
#define EPIC_MSG_INT0_DES_REG	(EPIC_CCSROFF + 0x11610)/* MSG INT0 Dest  */
#define EPIC_MSG_INT1_VEC_REG	(EPIC_CCSROFF + 0x11620)/* MSG INT1 vect/prio*/
#define EPIC_MSG_INT1_DES_REG	(EPIC_CCSROFF + 0x11630)/* MSG INT1 Dest  */
#define EPIC_MSG_INT2_VEC_REG	(EPIC_CCSROFF + 0x11640)/* MSG INT2 vect/prio*/
#define EPIC_MSG_INT2_DES_REG	(EPIC_CCSROFF + 0x11650)/* MSG INT2 Dest  */
#define EPIC_MSG_INT3_VEC_REG	(EPIC_CCSROFF + 0x11660)/* MSG INT3 vect/prio*/
#define EPIC_MSG_INT3_DES_REG	(EPIC_CCSROFF + 0x11670)/* MSG INT3 Dest  */

#define EPIC_P0_IPI_DPATCH_REG0	(EPIC_CCSROFF + 0x20040)/* P0 IPI0 dispatch */
#define EPIC_P0_IPI_DPATCH_REG1	(EPIC_CCSROFF + 0x20050)/* P0 IPI1 dispatch */
#define EPIC_P0_IPI_DPATCH_REG2	(EPIC_CCSROFF + 0x20060)/* P0 IPI2 dispatch */
#define EPIC_P0_IPI_DPATCH_REG3	(EPIC_CCSROFF + 0x20070)/* P0 IPI3 dispatch */
#define EPIC_P0_CTASK_PRI_REG	(EPIC_CCSROFF + 0x20080)/* P0 Cur Task Prio */
#define EPIC_P0_WHO_AM_I_REG	(EPIC_CCSROFF + 0x20090)/* P0 Who am I */
#define EPIC_P0_INT_ACK_REG	(EPIC_CCSROFF + 0x200a0)/* P0 Int Ack */
#define EPIC_P0_EOI_REG		(EPIC_CCSROFF + 0x200b0)/* P0 End of Int */

#if 0
#define EPIC_DUART1_INT_VEC_REG EPIC_IN_INT26_VEC_REG
#define EPIC_DUART1_INT_DES_REG EPIC_IN_INT26_DES_REG
#define EPIC_DUART2_INT_VEC_REG EPIC_IN_INT27_VEC_REG
#define EPIC_DUART2_INT_DES_REG EPIC_IN_INT27_DES_REG
#endif  /* 0 */

#if FALSE
#define EPIC_PROC_CTASK_PRI_REG (EPIC_CCSROFF + 0x00080)/* Proc. current task*/
#define EPIC_PROC_INT_ACK_REG	(EPIC_CCSROFF + 0x000a0)/* Int. acknowledge */
#define EPIC_PROC_EOI_REG	(EPIC_CCSROFF + 0x000b0)/* End of interrupt */
#endif  /* FALSE */

#define EPIC_EX_VEC_REG_INTERVAL	0x20	/* ex vector regs distance */
#define EPIC_IN_VEC_REG_INTERVAL	0x20	/* in vector regs distance */
#define EPIC_GT_VEC_REG_INTERVAL	0x40	/* tm vector regs distance */
#define EPIC_MSG_VEC_REG_INTERVAL	0x20	/* msg vector regs distance */
#define EPIC_IPI_VEC_REG_INTERVAL	0x10	/* ipi vector regs distance */

#define EPIC_EX_DEST_REG_VECREGOFF	0x10	/* EIDR offset from vec reg */
#define EPIC_IN_DEST_REG_VECREGOFF	0x10	/* IIDR offset from vec reg */
#define EPIC_MSG_DEST_REG_VECREGOFF	0x10	/* MIDR offset from vec reg */

#define EPIC_EX_VEC_REG(irq)     (EPIC_EX_INT0_VEC_REG + \
                                 ((irq) * EPIC_EX_VEC_REG_INTERVAL))

#define EPIC_IN_VEC_REG(irq)     (EPIC_IN_INT0_VEC_REG + \
                                 ((irq) * EPIC_IN_VEC_REG_INTERVAL))

#define EPIC_GT_VEC_REG(irq)     (EPIC_TM0_VEC_REG + \
                                 ((irq) * EPIC_GT_VEC_REG_INTERVAL))

#define EPIC_MSG_VEC_REG(irq)    (EPIC_MSG_INT0_VEC_REG + \
                                 ((irq) * EPIC_MSG_VEC_REG_INTERVAL))

#define EPIC_IPI_VEC_REG(irq)    (EPIC_IPI_0_VEC_REG + \
                                 ((irq) * EPIC_IPI_VEC_REG_INTERVAL))

#define EPIC_EX_DEST_REG(irq)    (EPIC_EX_VEC_REG(irq) + \
                                  EPIC_EX_DEST_REG_VECREGOFF)
#define EPIC_IN_DEST_REG(irq)    (EPIC_IN_VEC_REG(irq) + \