syslib.c

MPC8560 for vxwork BSP

* ERRNO
*/

void sysDelay (void)
    {
    sysMsDelay (1);
    }


#ifdef INCLUDE_CACHE_SUPPORT
/***********************************************************************
*
* sysL1CacheQuery - populate L1 cache size
*
* This routine populates L1 cache size and alignment from
* configuration registers.
*
* RETURNS : NONE
*
* ERRNO
*/

LOCAL void sysL1CacheQuery()
    {
    UINT32 temp;
    UINT32 align;
    UINT32 cachesize;

    temp = vxL1CFG0Get();

    cachesize = (temp & 0xFF) << 10;

    align = (temp >> 23) & 0x3;


    switch (align)
        {
        case 0:
            ppcE500CACHE_ALIGN_SIZE=32;
            break;
        case 1:
            ppcE500CACHE_ALIGN_SIZE=64;
            break;
        default:
            ppcE500CACHE_ALIGN_SIZE=32;
            break;
        }

    ppcE500DCACHE_LINE_NUM = (cachesize / ppcE500CACHE_ALIGN_SIZE);
    ppcE500ICACHE_LINE_NUM = (cachesize / ppcE500CACHE_ALIGN_SIZE);

    /* The core manual suggests for a 32 byte cache line and 8 lines per set 
       we actually need 12 unique address loads to flush the set. 
       The number of lines to flush should be ( 3/2 * cache lines ) */
    ppcE500DCACHE_LINE_NUM = (3*ppcE500DCACHE_LINE_NUM)>>1;
    ppcE500ICACHE_LINE_NUM = (3*ppcE500ICACHE_LINE_NUM)>>1;

    }
#endif /* INCLUDE_CACHE_SUPPORT */


/***************************************************************************
*
* vxImmrGet - get the CPM DP Ram base address
*
* This routine returns the CPM DP Ram base address for CPM device drivers.
*
* RETURNS:
*
* ERRNO
*/

UINT32 vxImmrGet (void)
    {
    return (CCSBAR + 0x80000);
    }


/***************************************************************************
*
* saveExcMsg - write exception message to save area for catastrophic error
*
* The message will be displayed upon rebooting with a bootrom.
*
* RETURNS: N/A
*
* ERRNO
*/

void saveExcMsg (
    char *errorMsg
    )
    {
    strcpy ((char *)EXC_MSG_OFFSET, errorMsg);
    }


void chipErrataCpu29Print(void)
    {
    saveExcMsg("Silicon fault detected, possible machine state corruption.\nSystem rebooted to limit damage.");
    }

void ddrDeviceIntHandler(void)
    {
    saveExcMsg("ECC fault detected, possible machine state corruption.\nSystem rebooted to limit damage.");
    sysToMonitor(BOOT_NO_AUTOBOOT);
    }


#ifdef INCLUDE_SYS_HW_INIT_0
IMPORT BOOL excExtendedVectors;
/***************************************************************************
*
* SYS_HW_INIT_0 - test for extended vectors
*
* This routine is used for testing extended vectors.
*
* RETURNS: N/A
*
* ERRNO
*/

void SYS_HW_INIT_0 (void)
    {
    excExtendedVectors = TRUE;
    }
#endif  /* INCLUDE_SYS_HW_INIT_0 */


#ifdef _GNU_TOOL
/*
*
* To avoid symbol loading error when BSP is compiled with GCC, the
* following dummy functions and variable are declared here.
*/
void sysIntHandler (void)
    {
    }

void vxDecInt (void)
    {
    }

int excRtnTbl = 0;
#endif  /* _GNU_TOOL */


#ifdef INCLUDE_SHOW_ROUTINES
/***************************************************************************
*
* coreLbcShow - show routine for local bus controller
*
* This routine displays the data for the local bus controller.
*
* RETURNS: NONE
*
* ERRNO
*/

void coreLbcShow(void)
    {
    VINT32 tmp, tmp2;

    tmp = * (VINT32 *) M85XX_BR0(CCSBAR);
    tmp2 = * (VINT32 *) M85XX_OR0(CCSBAR);
    printf("Local bus BR0 = 0x%x\tOR0 = 0x%x\n", tmp, tmp2);

    tmp = * (VINT32 *) M85XX_BR1(CCSBAR);
    tmp2 = * (VINT32 *) M85XX_OR1(CCSBAR);
    printf("Local bus BR1 = 0x%x\tOR1 = 0x%x\n", tmp, tmp2);

    tmp = * (VINT32 *) M85XX_BR2(CCSBAR);
    tmp2 = * (VINT32 *) M85XX_OR2(CCSBAR);
    printf("Local bus BR2 = 0x%x\tOR2 = 0x%x\n", tmp, tmp2);

    tmp = * (VINT32 *) M85XX_BR3(CCSBAR);
    tmp2 = * (VINT32 *) M85XX_OR3(CCSBAR);
    printf("Local bus BR3 = 0x%x\tOR3 = 0x%x\n", tmp, tmp2);

    tmp = * (VINT32 *) M85XX_BR4(CCSBAR);
    tmp2 = * (VINT32 *) M85XX_OR4(CCSBAR);
    printf("Local bus BR4 = 0x%x\tOR4 = 0x%x\n", tmp, tmp2);

    tmp = * (VINT32 *) M85XX_BR5(CCSBAR);
    tmp2 = * (VINT32 *) M85XX_OR5(CCSBAR);
    printf("Local bus BR5 = 0x%x\tOR5 = 0x%x\n", tmp, tmp2);

    tmp = * (VINT32 *) M85XX_BR6(CCSBAR);
    tmp2 = * (VINT32 *) M85XX_OR6(CCSBAR);
    printf("Local bus BR6 = 0x%x\tOR6 = 0x%x\n", tmp, tmp2);

    tmp = * (VINT32 *) M85XX_BR7(CCSBAR);
    tmp2 = * (VINT32 *) M85XX_OR7(CCSBAR);
    printf("Local bus BR7 = 0x%x\tOR7 = 0x%x\n", tmp, tmp2);

    tmp = * (VINT32 *) M85XX_LBCR(CCSBAR);
    printf("Local bus LBCR = 0x%x\n", tmp);

    tmp = * (VINT32 *) M85XX_LCRR(CCSBAR);
    printf("Local bus LCRR = 0x%x\n", tmp);
    }

#define xbit0(x, n)    ((x & (1 << (31 - n))) >> (31 - n))  /* 0..31 */
#define xbit32(x, n)   ((x & (1 << (63 - n))) >> (63 - n))  /* 32..63 */

/***************************************************************************
*
* coreShow - show routine for core registers
*
* This routine displays the core registers.
*
* RETURNS: NONE
*
* ERRNO
*/

void coreShow(void)
    {
    VUINT32 tmp, tmp2;

    printf("System: %s\t\n", sysModel() );
    printf("Core Speed: %3d MHz\t\tPlatform Speed: %3d MHz\n",
           sysCoreFreqGet()/1000000, sysClkFreqGet()/1000000 );

    tmp = vxMsrGet();
    printf("MSR - 0x%x\n", tmp);
    printf("      UCLE-%x SPE-%x WE-%x CE-%x EE-%x PR-%x ME-%x\n",
           xbit32(tmp,37), xbit32(tmp,38), xbit32(tmp,45), xbit32(tmp,46),
           xbit32(tmp,48), xbit32(tmp,49), xbit32(tmp,51));
    printf("      UBLE-%x DE-%x IS-%x DS-%x PMM-%x\n",
           xbit32(tmp,53), xbit32(tmp,54), xbit32(tmp,58), xbit32(tmp,59),
           xbit32(tmp,61));
    tmp = vxHid0Get();
    tmp2 = vxHid1Get();
    printf("HID0 = 0x%x, HID1 = 0x%x\n", tmp, tmp2);
    tmp = vxL1CSR0Get();
    printf("L1CSR0: Dcache is %s - 0x%x\n", tmp&1?"ON":"OFF", tmp);
    tmp = vxL1CSR1Get();
    printf("L1CSR1: Icache is %s - 0x%x\n", tmp&1?"ON":"OFF", tmp);
    tmp = vxL1CFG0Get();
    tmp2 = vxL1CFG1Get();
    printf("L1CFG0 = 0x%x, L1CFG1 = 0x%x\n", tmp, tmp2);
    tmp = *(VUINT32 *) (CCSBAR + 0x20000);
    printf("L2CTL - 0x%x\n", tmp);
    printf("        l2 is %s\n", tmp&0x80000000?"ON":"OFF");
    printf("        l2siz-%x l2blksz-%x l2do-%x l2io-%x\n",
           (xbit0(tmp,2)<<1)|xbit0(tmp,3), (xbit0(tmp,4)<<1)|xbit0(tmp,5),
           xbit0(tmp,9), xbit0(tmp,10));
    printf("        l2pmextdis-%x l2intdis-%x l2sram-%x\n",
           xbit0(tmp,11), xbit0(tmp,12),
           (xbit0(tmp,13)<<2)|(xbit0(tmp,14)<<1)|xbit0(tmp,15));
    tmp = *(VUINT32 *) (CCSBAR + 0x20100);
    tmp2 = *(VUINT32 *) (CCSBAR + 0x20108);
    printf("L2SRBAR0 - 0x%x\n", tmp);
    printf("L2SRBAR1 - 0x%x\n", tmp2);
    tmp = *(VUINT32 *) (CCSBAR + 0x0c08);
    tmp2 = *(VUINT32 *) (CCSBAR + 0x0c10);
    printf("LAWBAR0 = 0x%8x\t LAWAR0 = 0x%8x\n", tmp, tmp2);
    tmp = *(VUINT32 *) (CCSBAR + 0x0c28);
    tmp2 = *(VUINT32 *) (CCSBAR + 0x0c30);
    printf("LAWBAR1 = 0x%8x\t LAWAR1 = 0x%8x\n", tmp, tmp2);
    tmp = *(VUINT32 *) (CCSBAR + 0x0c48);
    tmp2 = *(VUINT32 *) (CCSBAR + 0x0c50);
    printf("LAWBAR2 = 0x%8x\t LAWAR2 = 0x%8x\n", tmp, tmp2);
    tmp = *(VUINT32 *) (CCSBAR + 0x0c68);
    tmp2 = *(VUINT32 *) (CCSBAR + 0x0c70);
    printf("LAWBAR3 = 0x%8x\t LAWAR3 = 0x%8x\n", tmp, tmp2);
    tmp = *(VUINT32 *) (CCSBAR + 0x0c88);
    tmp2 = *(VUINT32 *) (CCSBAR + 0x0c90);
    printf("LAWBAR4 = 0x%8x\t LAWAR4 = 0x%8x\n", tmp, tmp2);
    tmp = *(VUINT32 *) (CCSBAR + 0x0ca8);
    tmp2 = *(VUINT32 *) (CCSBAR + 0x0cb0);
    printf("LAWBAR5 = 0x%8x\t LAWAR5 = 0x%8x\n", tmp, tmp2);
    tmp = *(VUINT32 *) (CCSBAR + 0x0cc8);
    tmp2 = *(VUINT32 *) (CCSBAR + 0x0cd0);
    printf("LAWBAR6 = 0x%8x\t LAWAR6 = 0x%8x\n", tmp, tmp2);
    tmp = *(VUINT32 *) (CCSBAR + 0x0ce8);
    tmp2 = *(VUINT32 *) (CCSBAR + 0x0cf0);
    printf("LAWBAR7 = 0x%8x\t LAWAR7 = 0x%8x\n", tmp, tmp2);
    }
#endif  /* INCLUDE_SHOW_ROUTINES */

/* INT LINE TO IRQ assignment for wrSbc85xx-PCI board. */

LOCAL UCHAR sysPciIntRoute [NUM_PCI_SLOTS][4] = {

    /* slot 1 (dev 16 / 0x10) ; J4 */
    {PCI_XINT1_LVL, PCI_XINT2_LVL, PCI_XINT3_LVL, PCI_XINT4_LVL},

    /* slot 4 (dev 17 / 0x11) ; J5 */
    {PCI_XINT4_LVL, PCI_XINT1_LVL, PCI_XINT2_LVL, PCI_XINT3_LVL},

    /* slot 3 (dev 18 / 0x12) ; J6 */
    {PCI_XINT3_LVL, PCI_XINT4_LVL, PCI_XINT1_LVL, PCI_XINT2_LVL},

    /* slot 0 (dev 19 / 0x13, PMC) */
    {PCI_XINT1_LVL, PCI_XINT2_LVL, PCI_XINT3_LVL, PCI_XINT4_LVL},

    /* slot 2 (dev 23 / 0x17) ; J7 */
    {PCI_XINT2_LVL, PCI_XINT3_LVL, PCI_XINT4_LVL, PCI_XINT1_LVL},
};

/*******************************************************************************
*
* sysPciAutoconfigInclude - PCI autoconfig support routine
*
* RETURNS: OK or ERROR for the MPC106 or WINBOND devices.
*/

STATUS sysPciAutoconfigInclude
    (
    PCI_SYSTEM * pSys,			/* PCI_SYSTEM structure pointer */
    PCI_LOC * pLoc,			/* pointer to function in question */
    UINT devVend			/* deviceID/vendorID of device */
    )
    {
    
    /* Don't want to auto configure the bridge */ 
     if ( (devVend == PCI_DEV_ID_85XX) || (devVend == PCI_DEV_ID_82XX))
      return(ERROR);
 
    return OK; /* Autoconfigure all devices */
    }

/*******************************************************************************
*
* sysPciAutoconfigIntrAssign - PCI autoconfig support routine
*
* RETURNS: PCI interrupt line number given pin mask
*/

UCHAR sysPciAutoconfigIntrAssign
    (
    PCI_SYSTEM * pSys,			/* PCI_SYSTEM structure pointer */
    PCI_LOC * pLoc,			/* pointer to function in question */
    UCHAR pin				/* contents of PCI int pin register */
    )
    {
    UCHAR tmpChar = 0xff;

    /* 
     * Ensure this is a resonable value for bus zero.
     * If OK, return INT level, else we return 0xff.
     */
    if (((pin > 0) && (pin < 5))       				&& 
        ((pLoc->device) < 0x18)                         	&&
	(((pLoc->device) - PCI_SLOT1_DEVNO) >= 0))
	{
          int idx;
          
          idx = ((pLoc->device) - PCI_SLOT1_DEVNO); /* sebf */
          if (idx > NUM_PCI_SLOTS) idx = NUM_PCI_SLOTS - 1;
          
          tmpChar = sysPciIntRoute [idx] [(pin-1)];
	}

    /* return the value to be assigned to the pin */

    return (tmpChar);
    }

#if defined(INCLUDE_END)

/* locals */

#define MAC_ADRS_LEN 6
#define MAX_MAC_ADRS 4

/* include source */


/* globals */

unsigned char glbEnetAddr [MAX_MAC_ADRS][MAC_ADRS_LEN] = {
    { USR_MAC5, USR_MAC4, USR_MAC3a, WR_MAC2, WR_MAC1, WR_MAC0 },
    { USR_MAC5, USR_MAC4, USR_MAC3b, WR_MAC2, WR_MAC1, WR_MAC0 },
    { USR_MAC5, USR_MAC4, USR_MAC3c, WR_MAC2, WR_MAC1, WR_MAC0 },
    { USR_MAC5, USR_MAC4, USR_MAC3d, WR_MAC2, WR_MAC1, WR_MAC0 }
};

/***********************************************************************
*
* sysEnetAddrSet - sets the 6 byte ethernet address
*
* This routine sets the 6 byte ethernet address used by the ethernet device.
*
* RETURNS: N/A
*
* SEE ALSO: sysEnetAddrGet()
*/

void sysEnetAddrSet
    (
    UCHAR byte5,
    UCHAR byte4,
    UCHAR byte3,
    UCHAR byte2,
    UCHAR byte1,
    UCHAR byte0
    )
    {
    int unit = 0;

    glbEnetAddr[unit][5] = byte5;
    glbEnetAddr[unit][4] = byte4;
    glbEnetAddr[unit][3] = byte3;
    glbEnetAddr[unit][2] = byte2;
    glbEnetAddr[unit][1] = byte1;
    glbEnetAddr[unit][0] = byte0;

#ifdef INCLUDE_NV_RAM
#if (NV_RAM_SIZE != 0)

    sysNvRamSet ((char *)&glbEnetAddr[unit][0], MAC_ADRS_LEN,
                 NV_MAC_ADRS_OFFSET + unit * MAC_ADRS_LEN);

#endif /* (NV_RAM_SIZE != NONE) */
#endif  /* INCLUDE_NV_RAM */
    }

/***********************************************************************
*
* sysEnetAddrGet - gets the 6 byte ethernet address
*
* This routine gets the 6 byte ethernet address used by the ethernet device.
*
* RETURNS: OK
*
* SEE ALSO: sysEnetAddrSet()
*/

STATUS sysEnetAddrGet
    (
    int     unit,
    UCHAR * addr     /* where address is returned in */
    )
    {
    int n;
    UCHAR   addr2[MAC_ADRS_LEN];

    for (n = 0; n < MAC_ADRS_LEN; n++)
	 *(addr+n) = glbEnetAddr[unit][n];

    /* If NvRAM supported overwrite it with data from NvRAM */

#ifdef INCLUDE_NV_RAM
#if (NV_RAM_SIZE != 0)

    sysNvRamGet (&addr2[0], MAC_ADRS_LEN,
                 NV_MAC_ADRS_OFFSET + unit * MAC_ADRS_LEN);

    if (((addr2[5] != 0x00) || (addr2[4] != 0xa0) || (addr2[3] != 0x1e)) ||
        ((addr2[2] == 0xff) && (addr2[2] == 0xff) && (addr2[2] == 0xff)))
        {
        return (OK);  /* just use default add from glbEnetAddr[][] */
        }
    memcpy (addr, &addr2[0], MAC_ADRS_LEN);

#endif /* (NV_RAM_SIZE != NONE) */
#endif  /* INCLUDE_NV_RAM */

    return (OK);
    }

#endif /* INCLUDE_END */ 

/******************************************************************************
*
* sysSerialChanGet - get the SIO_CHAN device associated with a serial channel
*
* This routine gets the SIO_CHAN device associated with a specified serial
* channel.
*
* RETURNS: A pointer to the SIO_CHAN structure for the channel, or ERROR
* if the channel is invalid.
*/

#ifdef INCLUDE_SIO_UTILS
#define BSP_SERIAL_CHAN_GET	bspSerialChanGet
#else /* INCLUDE_SIO_UTILS */
#define BSP_SERIAL_CHAN_GET	sysSerialChanGet
#endif /* INCLUDE_SIO_UTILS */

SIO_CHAN *BSP_SERIAL_CHAN_GET 
    (
    int channel
    )
    {
    return((SIO_CHAN *)ERROR);
    }