syslib.c

MPC8560 for vxwork BSP

#  include "./sysNvRam.c"
#elif defined(INCLUDE_FLASH)
#  include "mem/flashMem.c"
#  include "mem/nvRamToFlash.c"
#else
#  include "mem/nullNvRam.c"
#endif  /* INCLUDE_NV_RAM || INCLUDE_FLASH */

#include "sysEpic.c"

#include "sysL2Cache.c"

#ifdef INCLUDE_CPM
#   include "mem/m82xxDpramLib.c"
#   include "m8560CpmIntrCtl.c"
#   ifdef INCLUDE_SCC_SERIAL
#       include "m8260Sio.c"
#       include "sysScc.c"
#   endif  /* INCLUDE_SCC_SERIAL */
#endif  /* INCLUDE_CPM */

#ifdef  INCLUDE_MOT_FCC_END
#   include "sysMotFcc2End.c"
#endif /* INCLUDE_MOT_FCC_END */

#ifdef INCLUDE_L1_IPARITY_HDLR
#   include "sysL1ICacheParity.c"
#endif


/* defines */

#define END_OF_TABLE	0
#define ZERO		0

#define DELTA(a,b)	(abs((int)a - (int)b))
#define HID0_MCP	0x80000000
#define HID1_ABE	0x00001000
#define HID1_ASTME	0x00002000


/* functions */

#if     defined (INCLUDE_SPE)
/*******************************************************************************
*
* sysSpeProbe - Check if the CPU has SPE unit.
*
* This routine returns OK it the CPU has an SPE unit in it.
* Presently it assumes available.
*
* RETURNS: OK 
*
* ERRNO
*/

int  sysSpeProbe (void)
    {
    ULONG regVal;
    int   speUnitPresent = OK;

     /* The CPU type is indicated in the Processor Version Register (PVR) */
 
     regVal = 0;

    switch (regVal)
        {
        case 0:
        default:
            speUnitPresent = OK;
            break;
        }      /* switch  */

    return (speUnitPresent);
    }
#endif  /* INCLUDE_SPE */


/******************************************************************************
*
* sysModel - return the model name of the CPU board
*
* This routine returns the model name of the CPU board.
*
* RETURNS: A pointer to the string.
*
* ERRNO
*/

char * sysModel (void)
    {
    UINT8 id;

    id = *(UINT8 *) UTIL_SR2;
    if ((id & BRD_SR2_8540SEL_MSK) == BRD_SR2_MODEL_8540)
        return(SYS_MODEL_8540);
    else
        return (SYS_MODEL_8560);
    }

/******************************************************************************
*
* sysBspRev - return the BSP version with the revision eg 1.0/<x>
*
* This function returns a pointer to a BSP version with the revision.
* for eg. 1.0/<x>. BSP_REV defined in config.h is concatenated to
* BSP_VERSION and returned.
*
* RETURNS: A pointer to the BSP version/revision string.
*
* ERRNO
*/

char * sysBspRev (void)
    {
    return (BSP_VERSION BSP_REV);
    }

/******************************************************************************
*
* sysCoreFreqGet - Determines the E500 Core Operating Frequency
*
* This routine returns the E500 Core Operating Frequency
*
* RETURNS: Core clock frequency in Hertz
*
* ERRNO
*/

UINT32 sysCoreFreqGet (void)
    {
    int coreRatio;

    coreRatio = M85XX_PORPLLSR_E500_RATIO(CCSBAR);
    switch (coreRatio)
        {
        case 4:
        case 5:
        case 6:
        case 7:
            return (sysClkFreqGet() * coreRatio >> 1);
        break;

        default:
            return (0);
        }
    }

/******************************************************************************
*
* sysClkFreqGet - Determines the CCB Operating Frequency
*
* This routine returns the CBB Operating Frequency.
*
* RETURNS: CCB clock frequency in Hertz
*
* ERRNO
*/

UINT32 sysClkFreqGet (void)
    {
    int platRatio;		/* all ratio values are x:1 */

    platRatio = M85XX_PORPLLSR_PLAT_RATIO(CCSBAR);
    switch (platRatio)
        {
        case 2:
        case 3:
        case 4:
        case 5:
        case 6:
        case 8:
        case 9:
        case 10:
        case 12:
        case 16:
            return (OSCILLATOR_FREQ * platRatio);
        break;

        default:
            return (0);
        }
    }

/******************************************************************************
*
* sysCpmFreqGet - Determines the CPM Operating Frequency
*
* This routine returns the CPM Operating Frequency.
* 
* RETURNS: CPM clock frequency in Hertz
*
* ERRNO
*/

UINT32 sysCpmFreqGet (void)
    {
    return  (sysClkFreqGet());	/* same as CCB freq */
    }

#ifdef INCLUDE_SCC_SERIAL
/******************************************************************************
*
* sysBaudClkFreq - Obtains frequency of the BRG_CLK in Hz
*
* From page 9-5 in Rev. 0 MPC8260 PowerQUICC II User's Manual
*
*     baud clock = 2*cpm_freq/2^2*(DFBRG+1) where DFBRG = 01
*                = 2*cpm_freq/16
*
* RETURNS: frequency of the BRG_CLK in Hz
*
* ERRNO
*/

int sysBaudClkFreq
    (
     void
    )
    {
    UINT32 cpmFreq = sysCpmFreqGet();

    if (cpmFreq == (UINT32) ERROR)
        return ERROR;
    else
        return cpmFreq*2/16;
    }
#endif  /* INCLUDE_SCC_SERIAL */

/******************************************************************************
*
* sysHwMemInit - initialize and configure system memory.
*
* This routine is called before sysHwInit(). It performs memory auto-sizing
* and updates the system's physical regions table, `sysPhysRgnTbl'. It may
* include the code to do runtime configuration of extra memory controllers.
*
* NOTE: This routine should not be called directly by the user application.  It
* cannot be used to initialize interrupt vectors.
*
* RETURNS: N/A
*
* ERRNO
*/

void sysHwMemInit (void)
    {
    static char * physTop;

    /* Call sysPhysMemTop() to do memory autosizing if available */

    physTop = sysPhysMemTop ();
    }

/******************************************************************************
*
* sysHwInit - initialize the system hardware
*
* This routine initializes various feature of the WR SBC85xx board. It sets up
* the control registers, initializes various devices if they are present.
*
* NOTE: This routine should not be called directly by the user.
*
* RETURNS: N/A
*
* ERRNO
*/

void sysHwInit (void)
    {

#ifdef INCLUDE_CPM
    UINT32 immrVal = vxImmrGet();
    memset((void *)(CCSBAR+0x80000),0,0x1000);
    m82xxDpramLibInit();

    /* Zero IO Port registers */
    /* reset the parallel ports */

    * M8260_IOP_PADIR(immrVal) = 0x00000000;
    * M8260_IOP_PAPAR(immrVal) = 0x00000000;
    * M8260_IOP_PASO(immrVal) = 0x00000000;
    * M8260_IOP_PAODR(immrVal) = 0x00000000;
    * M8260_IOP_PADAT(immrVal) = 0x00000000;

    * M8260_IOP_PBDIR(immrVal) = 0x00000000;
    * M8260_IOP_PBPAR(immrVal) = 0x00000000;
    * M8260_IOP_PBSO(immrVal) = 0x00000000;
    * M8260_IOP_PBODR(immrVal) = 0x00000000;
    * M8260_IOP_PBDAT(immrVal) = 0x00000000;

    * M8260_IOP_PCDIR(immrVal) = 0x00000000;
    * M8260_IOP_PCPAR(immrVal) = 0x00000000;
    * M8260_IOP_PCSO(immrVal) = 0x00000000;
    * M8260_IOP_PCODR(immrVal) = 0x00000000;
    * M8260_IOP_PCDAT(immrVal) = 0x00000000;

    * M8260_IOP_PDDIR(immrVal) = 0x00000000;
    * M8260_IOP_PDPAR(immrVal) = 0x00000000;
    * M8260_IOP_PDSO(immrVal) = 0x00000000;
    * M8260_IOP_PDODR(immrVal) = 0x00000000;
    * M8260_IOP_PDDAT(immrVal) = 0x00000000;
#endif  /* INCLUDE_CPM */

    /* Disable L1 Icache */
    sysL1Csr1Set(vxL1CSR1Get() & ~0x1);

    /* Put cachePpcReadOrigin at the start of data section */
    cachePpcReadOrigin = &_wrs_kernel_data_start;

    /* Enable machine check pin */
    vxHid0Set(vxHid0Get() | HID0_MCP);

#ifdef E500_L1_PARITY_RECOVERY
    /* Enable Parity in L1 caches */
    vxL1CSR0Set(vxL1CSR0Get() | _PPC_L1CSR_CPE);
    vxL1CSR1Set(vxL1CSR1Get() | _PPC_L1CSR_CPE);
#endif  /* E500_L1_PARITY_RECOVERY */

    sysTimerClkFreq = sysClkFreqGet() >> 3;	/* clock div is 8 */
    if (sysTimerClkFreq == 0)
        sysTimerClkFreq = PLAT_FREQ_DEFAULT >> 3;

    /* enable time base for delay use before DEC interrupt is setup */
    vxHid0Set(vxHid0Get() | _PPC_HID0_TBEN);

#ifdef INCLUDE_AUX_CLK
    sysAuxClkRateSet(254);
#endif

#ifdef INCLUDE_CACHE_SUPPORT
     sysL1CacheQuery(); 
#endif /* INCLUDE_CACHE_SUPPORT */

    /* Initialize L2CTL register */
    vxL2CTLSet(0x28000000, M85XX_L2CTL(CCSBAR));

    /* Need to setup static TLB entries for bootrom or any non-MMU 
     * enabled images */

    mmuE500TlbDynamicInvalidate();
    mmuE500TlbStaticInvalidate();
    mmuE500TlbStaticInit(sysStaticTlbDescNumEnt, &sysStaticTlbDesc[0], TRUE);

#if (!defined(INCLUDE_MMU_BASIC) && !defined(INCLUDE_MMU_FULL))
    mmuPpcIEnabled=TRUE;
    mmuPpcDEnabled=TRUE;
#else  /* !defined(INCLUDE_MMU_BASIC) && !defined(INCLUDE_MMU_FULL) */

    if (inFullVxWorksImage==FALSE)
        {
        mmuPpcIEnabled=TRUE;
        mmuPpcDEnabled=TRUE;
        }

#if (defined(USER_I_CACHE_ENABLE) && !defined(USER_I_MMU_ENABLE))
    /* Enable I Cache if instruction mmu disabled */
    mmuPpcIEnabled=TRUE;
#endif /* (defined(USER_I_CACHE_ENABLE) && !defined(USER_I_MMU_ENABLE)) */

#endif  /* !defined(INCLUDE_MMU_BASIC) && !defined(INCLUDE_MMU_FULL) */


#ifdef INCLUDE_SCC_SERIAL
    * M85XX_CPM_SCCR(CCSBAR) = BRGCLK_DIV_FACTOR;
#endif

#ifdef INCLUDE_CPM
    /* reset the Communications Processor */
    *M8260_CPCR(CCSBAR + 0x80000) = 0x80010000;
#ifdef  INCLUDE_SCC_SERIAL
    baudRateGenClk = 0xFDAD68;
#endif  /* INCLUDE_SCC_SERIAL */
#endif  /* INCLUDE_CPM */

#if (defined(INCLUDE_L2_CACHE) && defined(INCLUDE_CACHE_SUPPORT))
    vxHid1Set(vxHid1Get() | HID1_ABE );
    sysL2CacheInit();
#endif /* INCLUDE_L2_CACHE && INCLUDE_CACHE_SUPPORT*/

    vxHid1Set(vxHid1Get() | HID1_ASTME); /* Address streaming enable */

    /* Needed for the now obsolete NO_VX_BOOTROM */
    * (VINT32 *) M85XX_BR0(CCSBAR) = (VINT32) (BOOT_FLASH_ADRS | 0x0801);
    * (VINT32 *) M85XX_OR0(CCSBAR) = (VINT32) (BOOT_FLASH_ADRS | 0x0797);

#ifdef USE_ALT_BOOTLINE
    strcpy (BOOT_LINE_ADRS, altBootLine);
#endif

    /* Initialize the Embedded Programmable Interrupt Controller */
    sysEpicInit();

#ifdef INCLUDE_VXBUS
    hardWareInterFaceInit();
#endif /* INCLUDE_VXBUS */

#ifdef INCLUDE_SCC_SERIAL
    sysSerialHwInit();
#endif

    CACHE_PIPE_FLUSH();

    /* Get the Baud Rate Generator Clock frequency */

#ifdef INCLUDE_MOT_FCC_END
    sysFccEnetDisable (immrVal, 2);
#endif /* INCLUDE_MOT_FCC_END */

#ifdef E500_L1_PARITY_RECOVERY
    vxIvor1Set(_EXC_OFF_L1_PARITY);
#endif  /* E500_L1_PARITY_RECOVERY */
#ifdef INCLUDE_L1_IPARITY_HDLR
    installL1ICacheParityErrorRecovery();
#endif /* INCLUDE_L1_IPARITY_HDLR */

    /*
     * The power management mode is initialized here. Reduced power mode
     * is activated only when the kernel is idle (cf vxPowerDown).
     * Power management mode is selected via vxPowerModeSet().
     * DEFAULT_POWER_MGT_MODE is defined in config.h.
     */

    vxPowerModeSet (DEFAULT_POWER_MGT_MODE);

#ifdef INCLUDE_L2_SRAM
# if (defined(INCLUDE_CACHE_SUPPORT) && defined(INCLUDE_L2_CACHE))
    sysL2SramEnable(TRUE);
# else
    sysL2SramEnable(FALSE);
# endif
#endif  /* INCLUDE_L2_SRAM */
    }


#ifdef INCLUDE_L2_SRAM
/******************************************************************************
*
* sysL2SramEnable - enables L2SRAM if L2SRAM
*
* This routine enables L2SRAM if L2SRAM only or initializes blk size etc
* and leaves the rest to L2 cache code.
*
* RETURNS: N/A
*
* ERRNO
*/

LOCAL void sysL2SramEnable
    (
    BOOL both
    )
    {
    volatile int l2CtlVal;

    /* if INCLUDE_L2_CACHE and CACHE_SUPPORT */
    /* if ((L2_SRAM_SIZE + L2_CACHE_SIZE) > l2Siz) */
    /* Setup Windows for L2SRAM */    
    *(M85XX_L2SRBAR0(CCSBAR)) = (VUINT32)(L2SRAM_ADDR & M85XX_L2SRBAR_ADDR_MSK); 
    /* Get present value */
    l2CtlVal = vxL2CTLGet(M85XX_L2CTL(CCSBAR));

    /* Disable L2CTL initially to allow changing of block size */
    l2CtlVal&=(~M85XX_L2CTL_L2E_MSK);
    vxL2CTLSet(l2CtlVal,M85XX_L2CTL(CCSBAR));
    l2CtlVal &= ~M85XX_L2CTL_L2BLKSIZ_MSK;
    l2CtlVal &= ~M85XX_L2CTL_L2SRAM_MSK;

    if (both == TRUE)
        {
        /* Setup size of SRAM */
        l2CtlVal |= (L2SIZ_128KB << M85XX_L2CTL_L2BLKSIZ_BIT) | 
                    (0x2 << M85XX_L2CTL_L2SRAM_BIT);
        }
    else
        {
        l2CtlVal |= (L2SIZ_256KB << M85XX_L2CTL_L2BLKSIZ_BIT) | 
                    (0x1 << M85XX_L2CTL_L2SRAM_BIT);
        }

    /* Setup L2CTL for SRAM */
    vxL2CTLSet(l2CtlVal,M85XX_L2CTL(CCSBAR));

    if (both == FALSE)
        {
        /* This is done here so L2SRAM is set before enable */
        l2CtlVal |= M85XX_L2CTL_L2E_MSK; /* No cache so go ahead and enable */
        /* Enable L2CTL for SRAM */
        vxL2CTLSet(l2CtlVal,M85XX_L2CTL(CCSBAR));
        }
    }
#endif /* INCLUDE_L2_SRAM */