syslib.c

MPC8560 for vxwork BSP

/* sysLib.c - Wind River SBC 85xx board system-dependent library */

/* Copyright 1984-2004 Wind River Systems, Inc. */

/*
modification history
--------------------
02j,28Jul06,tor  Modified for VxBus
02i,06feb06,wap  Don't include sysMotTsecEnd.c in HEND case
02h,27jan06,wap  Fix command line builds with TSEC driver
02g,06jan06,wap  invoke vxbDevConnect() via taskSpawn()
02f,03jan06,wap  Allow command line build with vxBus support 
02e,13dec05,pch  SPR 113596: networking dependencies
02d,28oct05,mdo  SPR#114197 - protect against multiple defines for
                 INCLUDE_PCICFG_SHOW
02c,13sep05,to   add vxb prefix, vxbus cleanups.
02b,08aug05,mdo  Change WINDBUS to VXBUS
02a,10jan05,mil  Added support for INCLUDE_ECC.
01z,19nov04,mil  Added enabling of Icache when Immu is not enabled.
01y,11nov04,dtr  Adding user mode access for system memory.
01x,21oct04,dtr  Move ASTME enable outside L2 conditional.
01w,15oct04,mdo  SPR 98956, SPR #98944 - intLock in sysToMonitor
01v,04oct04,mdo  Documentation fixes for apigen
01u,27sep04,mil  Added cacheTextUpdate for _EXC_OFF_L1_PARITY after install.
01t,10sep04,mil  Changed macro L1_ERRATA_FIX_REV2 to INCLUDE_L1_IPARITY_HDLR.
01s,19aug04,dtr  Mod for ICacheParity handler.
01r,28jul04,mil  Added saveExcMsg for reboot error display.
01q,14jul04,mil  Fixed sysMsDelay accuracy, removed HID1[RFXE].
01p,08jul04,mil  Added setting of HID1[RFXE].
01o,18aug04,md   PM_RESERVED_MEM is dependent on INCLUDE_EDR_PM
01n,10jun04,mil  Added L1 errata workaround.
01m,09jun04,mil  Added writethrough cache mode for parity recovery.
01l,01jun04,mil  Fixed L2 not enabled by default.
01k,05may04,mil  Changed TLB mappings and various updates.
01j,02feb04,mil  Added enabling of HID1 bits.
01i,24oct03,mil  Cleanup.
01h,12sep03,mil  Updated TLB entries and added clock sensing, among others.
01g,20aug03,dtr  Adding in TSEC configlette file.
                 Adding new FCC2 End driver support.
                 Test for bootrom then initialise static TLB entries.
                 Adding dynamic config of L1 cache.
01f,04aug03,dtr  Adding in support for LBC SDRAM.
01e,29jul03,dtr  Removing CCSBAR magic number,support for MMU 'off' and
                 support for SNOOP when MMU 'off'.
01d,24jul03,mil  Added storing of flash params.
01c,19jun03,mil  Changed ROM TLB entry to writable, added SCC and FCC.
01b,07jan03,dtr  Adding TLB static table entries.
01a,13oct02,dtr  More complete file for further development.
*/

/*
DESCRIPTION
This library provides board-specific routines for WRSBC85XX.

INCLUDE FILES: sysLib.h

SEE ALSO:
.pG "Configuration"
*/

/* includes */

#include <vxWorks.h>
#include <vme.h>
#include <memLib.h>
#include <cacheLib.h>
#include <sysLib.h>
#include <config.h>
#include <string.h>
#include <intLib.h>
#include <logLib.h>
#include <stdio.h>
#include <taskLib.h>
#include <vxLib.h>
#include <tyLib.h>
#include <arch/ppc/mmuE500Lib.h>
#include <arch/ppc/vxPpcLib.h>
#include <private/vmLibP.h>
#include <miiLib.h>

#ifdef	INCLUDE_SPE
#   include "speLib.h"
#endif	/* INCLUDE_SPE */

#ifdef INCLUDE_CPM
#   include "drv/parallel/m8260IOPort.h"
#   include "drv/sio/m8260Cp.h"
#   include "drv/sio/m8260Scc.h"
#   include "drv/sio/m8260CpmMux.h"
#   include "m8560CpmIntrCtl.h"
#endif  /* INCLUDE_CPM */

#ifdef INCLUDE_VXBUS
#    include "hwif/vxbus/vxBus.h"
#    include "hwconf.c"
#ifndef PRJ_BUILD
#    include "cmdLine.c"
#endif /* PRJ_BUILD */
#endif /* INCLUDE_VXBUS */

#include <drv/pci/pciConfigLib.h>
#include <drv/pci/pciAutoConfigLib.h>
#include <drv/pci/pciIntLib.h>

/* globals */

TLB_ENTRY_DESC sysStaticTlbDesc [] =
{
    /* effAddr,  Unused,  realAddr, ts | size | attributes | permissions */

    {
    /* 16 MB (8 real) of boot flash, needed be FIRST entry here */
    BOOT_FLASH_MAP_ADRS, 0x0, BOOT_FLASH_MAP_ADRS,
    _MMU_TLB_TS_0 | _MMU_TLB_SZ_16M | _MMU_TLB_IPROT | 
#ifdef INCLUDE_TFFS  /* writable when using TFFS */
    _MMU_TLB_PERM_W | _MMU_TLB_PERM_X | _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G | \
    _MMU_TLB_ATTR_M
#else /* INCLUDE_TFFS */
    _MMU_TLB_PERM_X | _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G | _MMU_TLB_ATTR_M
#endif /* INCLUDE_TFFS */
    }
    ,
    {
    /* 2x256 MB of DDR RAM, two entries because 256 max, needed be SECOND */
    DDR_SDRAM_ADRS1, 0x0, DDR_SDRAM_ADRS1,
    _MMU_TLB_TS_0 | _MMU_TLB_SZ_256M | _MMU_TLB_IPROT | 
#ifdef  SW_MMU_ENABLE
#if (SW_MMU_ENABLE == 1)
    _MMU_TLB_PERM_UR | _MMU_TLB_PERM_UW | _MMU_TLB_PERM_UX | 
#endif
#endif  /* SW_MMU_ENABLE */
    _MMU_TLB_PERM_W | _MMU_TLB_PERM_X | CAM_DRAM_CACHE_MODE
    }
    ,
    {
    /* 2x256 MB of DDR RAM, 2nd half */
    DDR_SDRAM_ADRS2, 0x0, DDR_SDRAM_ADRS2,
    _MMU_TLB_TS_0 | _MMU_TLB_SZ_256M | _MMU_TLB_IPROT |
#ifdef  SW_MMU_ENABLE
#if (SW_MMU_ENABLE == 1)
    _MMU_TLB_PERM_UR | _MMU_TLB_PERM_UW | _MMU_TLB_PERM_UX | 
#endif
#endif  /* SW_MMU_ENABLE */
    _MMU_TLB_PERM_W | _MMU_TLB_PERM_X | CAM_DRAM_CACHE_MODE
    }
    ,
    {
    /* 1 MB of CCSRBAR area, TS=0 */
    CCSBAR, 0x0, CCSBAR,
    _MMU_TLB_TS_0 | _MMU_TLB_SZ_1M | _MMU_TLB_IPROT |
    _MMU_TLB_PERM_W | _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G | _MMU_TLB_ATTR_M
    }
    ,
    {
    /* 16(12) MB of WR SBC 85XX util area */ 
    UTIL_ADRS, 0x0, UTIL_ADRS,
    _MMU_TLB_TS_0 | _MMU_TLB_SZ_16M | _MMU_TLB_IPROT |
    _MMU_TLB_PERM_W | _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G | _MMU_TLB_ATTR_M
    }
#ifdef INCLUDE_LOCAL_SDRAM
    ,
    {
    /* 2x64 MB of LBC SDRAM, 1st half */
    LOCAL_SDRAM1_ADRS, 0x0, LOCAL_SDRAM1_ADRS,
    _MMU_TLB_TS_0 | _MMU_TLB_SZ_64M |
#ifdef  SW_MMU_ENABLE
#if (SW_MMU_ENABLE == 1)
    _MMU_TLB_PERM_UR | _MMU_TLB_PERM_UW | _MMU_TLB_PERM_UX | 
#endif
#endif  /* SW_MMU_ENABLE */
    _MMU_TLB_PERM_W | _MMU_TLB_PERM_X | CAM_DRAM_CACHE_MODE
    }
    ,
    {
    /* 2x64 MB of LBC SDRAM, 2nd half */
    LOCAL_SDRAM2_ADRS, 0x0, LOCAL_SDRAM2_ADRS,
    _MMU_TLB_TS_0 | _MMU_TLB_SZ_64M |
#ifdef  SW_MMU_ENABLE
#if (SW_MMU_ENABLE == 1)
    _MMU_TLB_PERM_UR | _MMU_TLB_PERM_UW | _MMU_TLB_PERM_UX | 
#endif
#endif  /* SW_MMU_ENABLE */
    _MMU_TLB_PERM_W | _MMU_TLB_PERM_X | CAM_DRAM_CACHE_MODE
    }
#endif  /* INCLUDE_LOCAL_SDRAM */
#ifdef INCLUDE_USR_FLASH
    ,
    {
    /* 2x64 MB of LBC flash, 1st half */
    USR_FLASH1_ADRS, 0x0, USR_FLASH1_ADRS,
    _MMU_TLB_TS_0 | _MMU_TLB_SZ_64M |
#ifdef INCLUDE_TFFS  /* writable when using TFFS */
    _MMU_TLB_PERM_W | _MMU_TLB_PERM_X | _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G | \
    _MMU_TLB_ATTR_M
#else /* INCLUDE_TFFS */
    _MMU_TLB_PERM_X | _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G | _MMU_TLB_ATTR_M
#endif /* INCLUDE_TFFS */
    }
    ,
    {
    /* 2x64 MB of LBC flash, 2nd half */
    USR_FLASH2_ADRS, 0x0, USR_FLASH2_ADRS,
    _MMU_TLB_TS_0 | _MMU_TLB_SZ_64M |
#ifdef INCLUDE_TFFS  /* writable when using TFFS */
    _MMU_TLB_PERM_W | _MMU_TLB_PERM_X | _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G | \
    _MMU_TLB_ATTR_M
#else /* INCLUDE_TFFS */
    _MMU_TLB_PERM_X | _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G | _MMU_TLB_ATTR_M
#endif /* INCLUDE_TFFS */
    }
#endif  /* INCLUDE_USR_FLASH */
    ,
    {
    /* 256 KB of L2SRAM */
    L2SRAM_ADDR, 0x0, L2SRAM_ADDR,
    _MMU_TLB_TS_0 | _MMU_TLB_SZ_256K |
    _MMU_TLB_PERM_W | _MMU_TLB_PERM_X | _MMU_TLB_ATTR_I
    }
    ,
    /* PCI */
    {
    PCI_MEM_ADRS, 0x0, PCI_MEM_ADRS, _MMU_TLB_TS_0 | _MMU_TLB_SZ_16M |
    _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G | _MMU_TLB_PERM_W
    },
    {
    PCI_MEMIO_ADRS, 0x0, PCI_MEMIO_ADRS, _MMU_TLB_TS_0 | _MMU_TLB_SZ_16M |
    _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G | _MMU_TLB_PERM_W
    },
    {
    PCI_IO_ADRS, 0x0, PCI_IO_ADRS, _MMU_TLB_TS_0 | _MMU_TLB_SZ_16M |
    _MMU_TLB_ATTR_I | _MMU_TLB_ATTR_G | _MMU_TLB_PERM_W
    }

};  /* end of sysStaticTlbDesc[] */

int sysStaticTlbDescNumEnt = NELEMENTS (sysStaticTlbDesc);


/*
 * sysPhysMemDesc[] is used to initialize the Page Table Entry (PTE) array
 * used by the MMU to translate addresses with single page (4k) granularity.
 * The MINIMUM recommended Page Table sizes for 32-bit PowerPCs are:
 *
 * Total mapped memory		Page Table size
 * -------------------		---------------
 *        8 Meg			     64 K
 *       16 Meg			    128 K
 *       32 Meg			    256 K
 *       64 Meg			    512 K
 *      128 Meg			      1 Meg
 * 	.				.
 * 	.				.
 * 	.				.
 *
 * [Ref: Ch 7, PowerPC Microprocessor Family: The Programming Environments]
 *
 */

PHYS_MEM_DESC sysPhysMemDesc [] =
{
    {
    /* Vector Table and Interrupt Stack */
    /* Must be sysPhysMemDesc [0] to allow adjustment in sysHwInit() */

    (VIRT_ADDR) LOCAL_MEM_LOCAL_ADRS,
    (PHYS_ADDR) LOCAL_MEM_LOCAL_ADRS,
    RAM_LOW_ADRS,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | TLB_CACHE_MODE
    }
    ,
    {
    /* Must be sysPhysMemDesc [1] to allow adjustment in sysHwInit() */
    (VIRT_ADDR) RAM_LOW_ADRS,
    (PHYS_ADDR) RAM_LOW_ADRS,
    LOCAL_MEM_LOCAL_ADRS + LOCAL_MEM_SIZE -  RAM_LOW_ADRS,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | TLB_CACHE_MODE
    }
    ,
    {
    (VIRT_ADDR) BOOT_FLASH_MAP_ADRS,
    (PHYS_ADDR) BOOT_FLASH_MAP_ADRS,
    BOOT_FLASH_MAP_SIZE,
#ifdef INCLUDE_TFFS  /* writable when using TFFS */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | \
    VM_STATE_MASK_GUARDED | VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT | \
    VM_STATE_GUARDED      | VM_STATE_MEM_COHERENCY
#else /* INCLUDE_TFFS */
    VM_STATE_MASK_VALID | VM_STATE_MASK_CACHEABLE | \
    VM_STATE_MASK_GUARDED | VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID      | VM_STATE_CACHEABLE_NOT | \
    VM_STATE_GUARDED      | VM_STATE_MEM_COHERENCY
#endif /* INCLUDE_TFFS */
    }
    ,
    {
    (VIRT_ADDR) CCSBAR,
    (PHYS_ADDR) CCSBAR,
    0x100000,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | \
    VM_STATE_MASK_GUARDED | VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT | \
    VM_STATE_GUARDED      | VM_STATE_MEM_COHERENCY
    }
    ,
    {
    (VIRT_ADDR) UTIL_ADRS,
    (PHYS_ADDR) UTIL_ADRS,
    16 * 0x100000,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | \
    VM_STATE_MASK_GUARDED | VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT | \
    VM_STATE_GUARDED      | VM_STATE_MEM_COHERENCY
    }

#ifdef INCLUDE_LOCAL_SDRAM
    ,
    {
    (VIRT_ADDR) LOCAL_SDRAM1_ADRS,
    (PHYS_ADDR) LOCAL_SDRAM1_ADRS,
    (LOCAL_SDRAM2_ADRS - LOCAL_SDRAM1_ADRS) * 2,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | TLB_CACHE_MODE
    }
#endif  /* INCLUDE_LOCAL_SDRAM */

#ifdef INCLUDE_USR_FLASH
    ,
    {
    (VIRT_ADDR) USR_FLASH1_ADRS,
    (PHYS_ADDR) USR_FLASH1_ADRS,
    (USR_FLASH2_ADRS - USR_FLASH1_ADRS) * 2,
#ifdef INCLUDE_TFFS  /* writable when using TFFS */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | \
    VM_STATE_MASK_GUARDED | VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT | \
    VM_STATE_GUARDED      | VM_STATE_MEM_COHERENCY
#else /* INCLUDE_TFFS */
    VM_STATE_MASK_VALID | VM_STATE_MASK_CACHEABLE | \
    VM_STATE_MASK_GUARDED | VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID      | VM_STATE_CACHEABLE_NOT | \
    VM_STATE_GUARDED      | VM_STATE_MEM_COHERENCY
#endif /* INCLUDE_TFFS */
    }
#endif  /* INCLUDE_USR_FLASH */

    ,
    {
    (VIRT_ADDR) L2SRAM_ADDR,
    (PHYS_ADDR) L2SRAM_ADDR,
    256 * 1024,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    }
    ,
    /* PCI */
    {
    (VIRT_ADDR) PCI_MEM_ADRS,
    (PHYS_ADDR) PCI_MEM_ADRS,
    16 * 1024 * 1024,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | \
    VM_STATE_MASK_GUARDED | VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT | \
    VM_STATE_GUARDED      | VM_STATE_MEM_COHERENCY
    }
    ,
    {
    (VIRT_ADDR) PCI_MEMIO_ADRS,
    (PHYS_ADDR) PCI_MEMIO_ADRS,
    16 * 1024 * 1024,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | \
    VM_STATE_MASK_GUARDED | VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT | \
    VM_STATE_GUARDED      | VM_STATE_MEM_COHERENCY
    }
    ,
    {
    (VIRT_ADDR) PCI_IO_ADRS,
    (PHYS_ADDR) PCI_IO_ADRS,
    16 * 1024 * 1024,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | \
    VM_STATE_MASK_GUARDED | VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT | \
    VM_STATE_GUARDED      | VM_STATE_MEM_COHERENCY
    }

};  /* end of sysPhysMemDesc[] */

int sysPhysMemDescNumEnt = NELEMENTS (sysPhysMemDesc);


int	sysBus = BUS;			/* system bus type (VME_BUS, etc) */
int	sysCpu = CPU;			/* system CPU type (PPC8260) */
char	*sysBootLine = BOOT_LINE_ADRS;	/* address of boot line */
#ifdef	USE_ALT_BOOTLINE
char	*altBootLine = ALT_BOOT_LINE;	/* address of alt boot line */
#endif
char	*sysExcMsg = EXC_MSG_ADRS;	/* catastrophic message area */
int	sysProcNum;			/* processor number of this CPU */
int	sysFlags;				/* boot flags */
char	sysBootHost [BOOT_FIELD_LEN];	/* name of host from which we booted */
char	sysBootFile [BOOT_FIELD_LEN];	/* name of file from which we booted */
BOOL	sysVmeEnable = FALSE;		/* by default no VME */
UINT32	sysTimerClkFreq = PLAT_FREQ_DEFAULT >> 3;  /* clock div is 8 */
UINT32	inFullVxWorksImage = FALSE;
UINT32	ppcE500ICACHE_LINE_NUM = (128 * 12);
UINT32	ppcE500DCACHE_LINE_NUM = (128 * 12);
UINT32	ppcE500CACHE_ALIGN_SIZE = 32;

#ifdef  INCLUDE_SCC_SERIAL
UINT32	baudRateGenClk;
#endif  /* INCLUDE_SCC_SERIAL */

#ifdef  INCLUDE_MOT_FCC_END
/* Set the following array to a unique Ethernet hardware address.
 * The last 5 nibbles are board specific, initialized in sysHwInit
 */
unsigned char sysFccEnetAddr [2][6] =
    {
    {0x08, 0x00, 0x3e, 0x33, 0x02, 0x01},
    {0x08, 0x00, 0x3e, 0x33, 0x02, 0x02}
    };
#endif  /* INCLUDE_MOT_FCC_END */

/* forward declarations */

IMPORT  char    _wrs_kernel_data_start;
IMPORT	BOOL	mmuPpcIEnabled;
IMPORT	BOOL	mmuPpcDEnabled;
IMPORT	void	mmuE500TlbDynamicInvalidate ();
IMPORT	void	mmuE500TlbStaticInvalidate ();
IMPORT	void	mmuE500TlbStaticInit (int numDescs, 
				      TLB_ENTRY_DESC *pTlbDesc, 
				      BOOL cacheAllow);
#ifdef INCLUDE_BRANCH_PREDICTION
IMPORT	void	disableBranchPrediction ();
#endif  /* INCLUDE_BRANCH_PREDICTION */

IMPORT  void    sysL1Csr1Set(UINT32);
IMPORT  UINT    sysTimeBaseLGet(void);

#ifdef INCLUDE_L1_IPARITY_HDLR_INBSP
#define _EXC_OFF_L1_PARITY 0x1500
IMPORT void jumpIParity();
IMPORT void sysIvor1Set(UINT32);
UINT32 instrParityCount = 0;
#endif  /* INCLUDE_L1_IPARITY_HDLR_INBSP */

UINT32		sysClkFreqGet (void);
LOCAL	void	sysL1CacheQuery (void);
LOCAL	void	sysL2SramEnable (BOOL both);
void    chipErrataCpu29Print(void);
void    ddrDeviceIntHandler(void);

#ifdef  INCLUDE_VXBUS

IMPORT  void    hardWareInterFaceInit (void);

#ifdef INCLUDE_SIO_UTILS
IMPORT void    sysSerialConnectAll(void);
#endif /* INCLUDE_SIO_UTILS */

#endif  /* INCLUDE_VXBUS */

#ifdef	INCLUDE_SPE
IMPORT	int	(* _func_speProbeRtn) () ;
#endif	/* INCLUDE_SPE */

#ifdef INCLUDE_CPM
UINT32	vxImmrGet ();
void	m85xxCpmInt (void);
#ifdef  INCLUDE_MOT_FCC_END
STATUS	sysFccEnetAddrGet (int unit, UCHAR * address);
#endif  /* INCLUDE_MOT_FCC_END */
#endif  /* INCLUDE_CPM */

/* include BSP specific files */

#ifdef INCLUDE_PCI_BUS
#   include "pci/pciIntLib.c"           /* PCI int support */
#   include "pci/pciConfigLib.c"        /* pci configuration library */
#   ifdef INCLUDE_SHOW_ROUTINES
#       include "pci/pciConfigShow.c"   /* pci configuration show routines */
#   endif
#   include "pci/pciAutoConfigLib.c"    /* automatic PCI configuration */

#endif /* INCLUDE_PCI_BUS */

#include "m85xxTimer.c"

#if defined(INCLUDE_NV_RAM)