motfcc2end.c

MPC8560 for vxwork BSP

results in a duplex mis-match. This causes TX errors in the driver
and a reduction in throughput.
\cs
    FUNCPTR miiPhyBitRead;
\ce
\i MII Bit Read Function
This function pointer is initialized by the BSP and called by the driver.
The driver calls this function when it needs to read a bit from the MII
interface. The MII interface is hardware specific.
\cs
    FUNCPTR miiPhyBitWrite;
\ce
\i MII Bit Write Function
This function pointer is initialized by the BSP and called by the driver.
The driver calls this function when it needs to write a bit to the MII
interface. This MII interface is hardware specific.
\cs
    FUNCPTR miiPhyDuplex;
\ce
\i Duplex Status Call Back
This function pointer is initialized by the BSP and called by the driver.
The driver calls this function to obtain the status of the duplex
setting in the PHY.
\cs
    FUNCPTR miiPhySpeed;
\ce
\i Speed Status Call Back
This function pointer is initialized by the BSP and called by the driver.
The driver calls this function to obtain the status of the speed
setting in the PHY. This interface is hardware specific.
\cs
    FUNCPTR hbFail;
\ce
\i HeartBeat Fail Indicator
This function pointer is initialized by the BSP and called by the driver.
The driver calls this function to indicate an FCC heartbeat error.
\cs
    FUNCPTR intDisc;
\ce
\i Disconnect Function
This function pointer is initialized by the BSP and called by the driver.
The driver calls this function to indicate an FCC disconnect error.
\cs
    FUNCPTR dpramFree;
\ce
\i DPRAM Free routine
This function pointer is initialized by the BSP and called by the driver.
The BSP allocates memory for the BDs from this pool. The Driver must
free the BD area using this function.
\cs
    FUNCPTR dpramFccMalloc;
\ce
\i DPRAM FCC Malloc routine
This function pointer is initialized by the BSP and called by the driver.
The Driver allocates memory from the FCC specific POOL using this function.
\cs
    FUNCPTR dpramFccFree;
\ce
\i DPRAM FCC Free routine
This function pointer is initialized by the BSP and called by the driver.
The Driver frees memory from the FCC specific POOL using this function.
\ie

\i <maxRxFrames>
The <maxRxFrames> parameter is optional.  It limits the number 
of frames the receive handler services in one pass. It is intended to 
prevent the tNetTask from monopolizing the CPU and starving
applications. The default value is nRFDs * 2.

\ie

EXTERNAL SUPPORT REQUIREMENTS
This driver requires several external support functions.

\is
\i sysFccEnetEnable()
\cs
    STATUS sysFccEnetEnable (UINT32 immrVal, UINT8 fccNum);
\ce
This routine is expected to handle any target-specific functions needed
to enable the FCC. These functions typically include setting the Port B and C
on the MPC8260 so that the MII interface may be used. This routine is
expected to return OK on success, or ERROR. The driver calls this routine,
once per device, from the motFccStart () routine.
\i sysFccEnetDisable()
\cs
    STATUS sysFccEnetDisable (UINT32 immrVal, UINT8 fccNum);
\ce
This routine is expected to perform any target specific functions required
to disable the MII interface to the FCC.  This involves restoring the
default values for all the Port B and C signals. This routine is expected to
return OK on success, or ERROR. The driver calls this routine from the
motFccStop() routine each time a device is disabled.
\i sysFccEnetAddrGet()
\cs
    STATUS sysFccEnetAddrGet (int unit,UCHAR *address);
\ce
The driver expects this routine to provide the six-byte Ethernet hardware
address that is used by this device.  This routine must copy the six-byte
address to the space provided by <enetAddr>.  This routine is expected to
return OK on success, or ERROR.  The driver calls this routine, once per
device, from the motFccEndLoad() routine.
\cs
    STATUS sysFccMiiBitWr (UINT32 immrVal, UINT8 fccNum, INT32 bitVal);
\ce
This routine is expected to perform any target specific functions required
to write a single bit value to the MII management interface of a MII-compliant
PHY device. The MII management interface is made up of two lines: management
data clock (MDC) and management data input/output (MDIO). The former provides
the timing reference for transfer of information on the MDIO signal.
The latter is used to transfer control and status information between the
PHY and the FCC. For this transfer to be successful, the information itself
has to be encoded into a frame format, and both the MDIO and MDC signals have
to comply with certain requirements as described in the 802.3u IEEE Standard.
There is not built-in support in the FCC for the MII management interface.
This means that the clocking on the MDC line and the framing of the information
on the MDIO signal have to be done in software. Hence, this routine is
expected to write the value in <bitVal> to the MDIO line while properly
sourcing the MDC clock to a PHY, for one bit time.
\cs
    STATUS sysFccMiiBitRd (UINT32 immrVal, UINT8 fccNum, INT8 * bitVal);
\ce
This routine is expected to perform any target specific functions required
to read a single bit value from the MII management interface of a MII-compliant
PHY device. The MII management interface is made up of two lines: management
data clock (MDC) and management data input/output (MDIO). The former provides
the timing reference for transfer of information on the MDIO signal.
The latter is used to transfer control and status information between the
PHY and the FCC. For this transfer to be successful, the information itself
has to be encoded into a frame format, and both the MDIO and MDC signals have
to comply with certain requirements as described in the 802.3u IEEE Standard.
There is not built-in support in the FCC for the MII management interface.
This means that the clocking on the MDC line and the framing of the information
on the MDIO signal have to be done in software. Hence, this routine is
expected to read the value from the MDIO line in <bitVal>, while properly
sourcing the MDC clock to a PHY, for one bit time.
\ie


SYSTEM RESOURCE USAGE
If the driver allocates the memory for the BDs to share with the FCC,
it does so by calling the cacheDmaMalloc() routine. If this region is provided
by the user, it must be from non-cacheable memory. 

This driver can operate only if this memory region is non-cacheable
or if the hardware implements bus snooping.  The driver cannot maintain
cache coherency for the device because the BDs are asynchronously
modified by both the driver and the device, and these fields share
the same cache line.

If the driver allocates the memory for the data buffers to share with the FCC,
it does so by calling the memalign () routine.  The driver does not need to
use cache-safe memory for data buffers, since the host CPU and the device are
not allowed to modify buffers asynchronously. The related cache lines are
flushed or invalidated as appropriate.

TUNING HINTS

The only adjustable parameters are the number of TBDs and RBDs that are
created at run-time.  These parameters are given to the driver when
motFccEndLoad() is called.  There is one RBD associated with each received
frame, whereas a single transmit packet frequently uses more than one TBD.
For memory-limited applications, decreasing the number of RBDs may be
desirable.  Decreasing the number of TBDs below a certain point results
in substantial performance degradation, and is not recommended. Increasing
the number of buffer descriptors can boost performance.


SPECIAL CONSIDERATIONS

SEE ALSO: ifLib,
\tb MPC8260 Fast Ethernet Controller (Supplement to the MPC860 User's Manual) 
\tb Motorola MPC860 User's Manual ,

\INTERNAL
This driver contains conditional compilation switch MOT_FCC_DBG.
If defined, adds debug output routines.  Output is further
selectable at run-time via the motFccEndDbg global variable.
*/

#include "vxWorks.h"
#include "wdLib.h"
#include "iv.h"
#include "vme.h"
#include "net/mbuf.h"
#include "net/unixLib.h"
#include "net/protosw.h"
#include "sys/socket.h"
#include "sys/ioctl.h"
#include "errno.h"
#include "memLib.h"
#include "intLib.h"
#include "net/route.h"
#include "iosLib.h"
#include "errnoLib.h"
#include "vxLib.h"

#include "cacheLib.h"
#include "logLib.h"
#include "netLib.h"
#include "stdio.h"
#include "stdlib.h"
#include "sysLib.h"
#include "taskLib.h"

#include "net/systm.h"
#include "net/if_subr.h"

#undef ETHER_MAP_IP_MULTICAST
#include "etherMultiLib.h"
#include "end.h"

#define    END_MACROS
#include "endLib.h"
#include "miiLib.h"

#include "lstLib.h"
#include "semLib.h"
#include "sys/times.h"

#include "net/unixLib.h"
#include "net/if_subr.h"

#ifdef WR_IPV6
#include "adv_net.h"
#endif /* WR_IPV6 */

#include "drv/mem/m82xxDpramLib.h"
#include "drv/intrCtl/m8260IntrCtl.h"
#include "drv/end/m8260Fcc.h"
#include "drv/sio/m8260Cp.h"
#include "drv/sio/m8260CpmMux.h"

#ifndef _WRS_FASTTEXT
#define _WRS_FASTTEXT
#endif

#define _WRS_VXWORKS_VNUM \
    ((_WRS_VXWORKS_MAJOR << 16)|(_WRS_VXWORKS_MINOR << 8)|(_WRS_VXWORKS_MAINT))

#if _WRS_VXWORKS_VNUM >= 0x060100

#undef netJobAdd	/* for the cases we store it in a pointer */

#define NET_JOB_ADD(f, a1, a2, a3, a4, a5)			    \
    (jobQueueStdPost (&netJobInfo, NET_TASK_QJOB_PRI,		    \
		      (VOIDFUNCPTR)(f), (void *)(a1), (void *)(a2), \
		      (void *)(a3), (void *)(a4), (void *)(a5)))

#else
#define NET_JOB_ADD(f, a1, a2, a3, a4, a5)			    \
    netJobAdd ((f), (a1), (a2), (a3), (a4), (a5))
#endif

#undef MOT_FCC_DBG
#undef MOT_FCC_STAT_MONITOR

/* define if CPM-21 errata applies */
#define MOT_FCC_CPM_21_ERRATA

#ifndef MOTFCC2END_HEADER
#define MOTFCC2END_HEADER "drv/end/motFcc2End.h"
#endif

#include MOTFCC2END_HEADER

#ifdef INCLUDE_WINDVIEW
#undef INCLUDE_WINDVIEW
#endif

#undef INCLUDE_WINDVIEW

#ifdef  INCLUDE_WINDVIEW
/* WindView Event numbers */
#define WV_INT_ENTRY(b,l)            wvEvent(1000,b,l)
#define WV_INT_EXIT(b,l)             wvEvent(1001,b,l)
#define WV_INT_RXB_ENTRY(b,l)        wvEvent(1300,b,l)
#define WV_INT_RXF_ENTRY(b,l)        wvEvent(1310,b,l)
#define WV_INT_BSY_ENTRY(b,l)        wvEvent(1320,b,l)
#define WV_INT_BSY_EXIT(b,l)         wvEvent(1321,b,l)
#define WV_INT_RX_EXIT(b,l)          wvEvent(1301,b,l)
#define WV_INT_RXC_ENTRY(b,l)        wvEvent(1400,b,l)
#define WV_INT_RXC_EXIT(b,l)         wvEvent(1401,b,l)
#define WV_INT_TXC_ENTRY(b,l)        wvEvent(1500,b,l)
#define WV_INT_TXC_EXIT(b,l)         wvEvent(1501,b,l)
#define WV_INT_TXB_ENTRY(b,l)        wvEvent(1600,b,l)
#define WV_INT_TXB_EXIT(b,l)         wvEvent(1601,b,l)
#define WV_INT_TXE_ENTRY(b,l)        wvEvent(1610,b,l)
#define WV_INT_TXE_EXIT(b,l)         wvEvent(1611,b,l)
#define WV_INT_NETJOBADD_ENTRY(b,l)  wvEvent(1800,b,l)
#define WV_INT_NETJOBADD_EXIT(b,l)   wvEvent(1801,b,l)
#define WV_HANDLER_ENTRY(b,l)        wvEvent(2000,b,l)
#define WV_HANDLER_EXIT(b,l)         wvEvent(2001,b,l)
#define WV_MUX_TX_RESTART_ENTRY(b,l) wvEvent(2100,b,l)
#define WV_MUX_TX_RESTART_EXIT(b,l)  wvEvent(2101,b,l)
#define WV_MUX_ERROR_ENTRY(b,l)      wvEvent(2200,b,l)
#define WV_MUX_ERROR_EXIT(b,l)       wvEvent(2201,b,l)
#define WV_SEND_ENTRY(b,l)           wvEvent(5000,b,l)
#define WV_SEND_EXIT(b,l)            wvEvent(5001,b,l)
#define WV_RECV_ENTRY(b,l)           wvEvent(6000,b,l)
#define WV_RECV_EXIT(b,l)            wvEvent(6001,b,l)
#define WV_CACHE_FLUSH_ENTRY(b,l)    wvEvent(8000,b,l)
#define WV_CACHE_FLUSH_EXIT(b,l)     wvEvent(8001,b,l)
#define WV_CACHE_INVAL_ENTRY(b,l)    wvEvent(8100,b,l)
#define WV_CACHE_INVAL_EXIT(b,l)     wvEvent(8101,b,l)
#define WV_CACHE_DEBUG_ENTRY(b,l)    wvEvent(9999,b,l)
#endif

/* defines */

/*
 * Shifted buffer descriptor status bits. These values are
 * shifted 16-bits left for use in the combined bdStatLen field,
 * of which the high-order half-word contains the status. We
 * assume a big endian host (almost certainly PPC) throughout
 * this driver.
 */

#define M8260_FETH_TBDS_R	((UINT32)(M8260_FETH_TBD_R << 16))
#define M8260_FETH_TBDS_PAD	(M8260_FETH_TBD_PAD << 16)
#define M8260_FETH_TBDS_W	(M8260_FETH_TBD_W << 16)
#define M8260_FETH_TBDS_I	(M8260_FETH_TBD_I << 16)
#define M8260_FETH_TBDS_L	(M8260_FETH_TBD_L << 16)
#define M8260_FETH_TBDS_TC	(M8260_FETH_TBD_TC << 16)
#define M8260_FETH_TBDS_DEF	(M8260_FETH_TBD_DEF << 16)
#define M8260_FETH_TBDS_HB	(M8260_FETH_TBD_HB << 16)
#define M8260_FETH_TBDS_LC	(M8260_FETH_TBD_LC << 16)
#define M8260_FETH_TBDS_RL	(M8260_FETH_TBD_RL << 16)
#define M8260_FETH_TBDS_RC	(M8260_FETH_TBD_RC << 16)
#define M8260_FETH_TBDS_UN	(M8260_FETH_TBD_UN << 16)
#define M8260_FETH_TBDS_CSL	(M8260_FETH_TBD_CSL << 16)

#define M8260_FETH_RBDS_E	((UINT32)(M8260_FETH_RBD_E << 16))
#define M8260_FETH_RBDS_W	(M8260_FETH_RBD_W << 16)
#define M8260_FETH_RBDS_I	(M8260_FETH_RBD_I << 16)
#define M8260_FETH_RBDS_L	(M8260_FETH_RBD_L << 16)
#define M8260_FETH_RBDS_F	(M8260_FETH_RBD_F << 16)
#define M8260_FETH_RBDS_M	(M8260_FETH_RBD_M << 16)
#define M8260_FETH_RBDS_BC	(M8260_FETH_RBD_BC << 16)
#define M8260_FETH_RBDS_MC	(M8260_FETH_RBD_MC << 16)
#define M8260_FETH_RBDS_LG	(M8260_FETH_RBD_LG << 16)
#define M8260_FETH_RBDS_NO	(M8260_FETH_RBD_NO << 16)
#define M8260_FETH_RBDS_SH	(M8260_FETH_RBD_SH << 16)
#define M8260_FETH_RBDS_CR	(M8260_FETH_RBD_CR << 16)
#define M8260_FETH_RBDS_OV	(M8260_FETH_RBD_OV << 16)
#define M8260_FETH_RBDS_CL	(M8260_FETH_RBD_CL << 16)

#define MOT_FCC_RBDS_ERR	(MOT_FCC_RBD_ERR << 16)

/* Cache and virtual/physical memory related macros */

#define MOT_FCC_CACHE_INVAL(address, len) { \
        CACHE_DRV_INVALIDATE (&pDrvCtrl->bufCacheFuncs, (address), (len));  \
    }

#define MOT_FCC_CACHE_FLUSH(address, len) { \
        CACHE_DRV_FLUSH (&pDrvCtrl->bufCacheFuncs, (address), (len)); \
    }