rominit.s

MPC8560 for vxwork BSP

        /*
         * Rewrite TLB to set WINGE to 00000
         * TLB1 #1:  RAM - Protected, global, TS=0, cached
         * 0x00000000..0x0fffffff => 0x000000000..0x0fffffff (256 MB)
         * Attributes: UXSX-UWSW-URSR (all)
         */

	addis	r4, 0, 0x1001		/* TLBSEL = TLB1(CAM), ESEL = 1 */ 
	ori	r4, r4, 0x0000
	mtspr	MAS0, r4
	addis	r5, 0, 0xC000		/* V = 1, IPROT = 1, TID = 0 */
	ori	r5, r5, 0x0900		/* TS = 0, TSIZE = 256 MB */
	mtspr	MAS1, r5
	addis	r6, 0, DDR_SDRAM_ADRS1 >> 16	/* EPN = 0x00000000 */
	ori	r6, r6, 0x0000		/* WIMGE = 00000 */
	mtspr	MAS2, r6
	addis	r7, 0, DDR_SDRAM_ADRS1 >> 16	/* RPN = 0x00000000 */
	ori	r7, r7, 0x003f		/* UXSX-UWSW-URSR = 11-11-11 */
	mtspr	MAS3, r7
	tlbwe
	tlbsync

        /*
         * Rewrite TLB to set WINGE to 00000
         * TLB1 #2:  RAM - Protected, global, TS=0, cached
         * 0x10000000..0x1fffffff => 0x100000000..0x1fffffff (256 MB)
         * Attributes: UXSX-UWSW-URSR (all)
         */

	addis	r4, 0, 0x1002		/* TLBSEL = TLB1(CAM), ESEL = 2 */ 
	ori	r4, r4, 0x0000
	mtspr	MAS0, r4
	addis	r5, 0, 0xC000		/* V = 1, IPROT = 1, TID = 0 */
	ori	r5, r5, 0x0900		/* TS = 0, TSIZE = 256 MB */
	mtspr	MAS1, r5
	addis	r6, 0, DDR_SDRAM_ADRS2 >> 16	/* EPN = 0x10000000 */
	ori	r6, r6, 0x0000		/* WIMGE = 00000 */
	mtspr	MAS2, r6
	addis	r7, 0, DDR_SDRAM_ADRS2 >> 16	/* RPN = 0x10000000 */
	ori	r7, r7, 0x003f		/* UXSX-UWSW-URSR = 11-11-11 */
	mtspr	MAS3, r7
	tlbwe
	tlbsync

#if FALSE  /* not using L2SRAM in ROM */
	/* L2SRAM setup */
	WRITEADR(r6, r7, M85XX_L2CTL(CCSBAR), 0xa8010000)
	WRITEADR(r6, r7, M85XX_L2SRBAR0(CCSBAR), L2SRAM_ADDR)
#endif  /* FALSE */

#ifdef INCLUDE_LOCAL_SDRAM
	/* (re)map TLB that were not protected before (re)initialize */

        /*
         * TLB1 #5:  SDRAM - Global, TS=0, cached
         * 0x20000000..0x23ffffff => 0x200000000..0x23ffffff (64 MB)
         * Attributes: UXSX-UWSW-URSR (all)
         */

	addis	r4, 0, 0x1005		/* TLBSEL = TLB1(CAM), ESEL = 5 */ 
	ori	r4, r4, 0x0000
	mtspr	MAS0, r4
	addis	r5, 0, 0x8000		/* V = 1, IPROT = 0, TID = 0 */
	ori	r5, r5, 0x0800		/* TS = 0, TSIZE = 64 MB */
	mtspr	MAS1, r5
	addis	r6, 0, LOCAL_SDRAM1_ADRS >> 16	/* EPN = 0x20000000 */
	ori	r6, r6, 0x0006		/* WIMGE = 00110 */
	mtspr	MAS2, r6
	addis	r7, 0, LOCAL_SDRAM1_ADRS >> 16	/* RPN = 0x20000000 */
	ori	r7, r7, 0x003f		/* UXSX-UWSW-URSR = 11-11-11 */
	mtspr	MAS3, r7
	tlbwe
	tlbsync

        /*
         * TLB1 #6:  SDRAM - Global, TS=0, cached
         * 0x24000000..0x27ffffff => 0x240000000..0x27ffffff (64 MB)
         * Attributes: UXSX-UWSW-URSR (all)
         */

	addis	r4, 0, 0x1006		/* TLBSEL = TLB1(CAM), ESEL = 6 */ 
	ori	r4, r4, 0x0000
	mtspr	MAS0, r4
	addis	r5, 0, 0x8000		/* V = 1, IPROT = 0, TID = 0 */
	ori	r5, r5, 0x0800		/* TS = 0, TSIZE = 64 MB */
	mtspr	MAS1, r5
	addis	r6, 0, LOCAL_SDRAM2_ADRS >> 16	/* EPN = 0x24000000 */
	ori	r6, r6, 0x0006		/* WIMGE = 00110 */
	mtspr	MAS2, r6
	addis	r7, 0, LOCAL_SDRAM2_ADRS >> 16	/* RPN = 0x24000000 */
	ori	r7, r7, 0x003f		/* UXSX-UWSW-URSR = 11-11-11 */
	mtspr	MAS3, r7
	tlbwe
	tlbsync

	WRITEADR(r6, r7, M85XX_LSDMR(CCSBAR), 0x2862a527)
	WRITEADR(r6, r7, 0x20000000, 0xff)
	WRITEADR(r6, r7, 0x24000000, 0xff)
	mbar	0
	WRITEADR(r6, r7, M85XX_LSDMR(CCSBAR), 0x0862a527)
	WRITEADR(r6, r7, 0x20000000, 0xff)		/* DWR2_1 */
	WRITEADR(r6, r7, 0x24000000, 0xff)		/* DWR2_2 */
	WRITEADR(r6, r7, 0x20000000, 0xff)		/* DWR3_1 */
	WRITEADR(r6, r7, 0x24000000, 0xff)		/* DWR3_2 */
	WRITEADR(r6, r7, 0x20000000, 0xff)		/* DWR4_1 */
	WRITEADR(r6, r7, 0x24000000, 0xff)		/* DWR4_2 */
	WRITEADR(r6, r7, 0x20000000, 0xff)		/* DWR5_1 */
	WRITEADR(r6, r7, 0x24000000, 0xff)		/* DWR5_2 */
	WRITEADR(r6, r7, 0x20000000, 0xff)		/* DWR6_1 */
	WRITEADR(r6, r7, 0x24000000, 0xff)		/* DWR6_2 */
	WRITEADR(r6, r7, 0x20000000, 0xff)		/* DWR7_1 */
	WRITEADR(r6, r7, 0x24000000, 0xff)		/* DWR7_2 */
	WRITEADR(r6, r7, 0x20000000, 0xff)		/* DWR8_1 */
	WRITEADR(r6, r7, 0x24000000, 0xff)		/* DWR8_2 */
	WRITEADR(r6, r7, 0x20000000, 0xff)		/* DWR9_1 */
	WRITEADR(r6, r7, 0x24000000, 0xff)		/* DWR9_2 */
	WRITEADR(r6, r7, M85XX_LSDMR(CCSBAR), 0x1862a527)
	mbar	0
	WRITEADR(r6, r7, 0x20000000, 0xff)		/* DWR10_1 */
	WRITEADR(r6, r7, 0x24000000, 0xff)		/* DWR10_2 */
	WRITEADR(r6, r7, M85XX_LSDMR(CCSBAR), 0x4062a527)
	mbar	0

        /*
         * Change WIMGE
         * TLB1 #5:  SDRAM - Global, TS=0, cached
         * 0x20000000..0x23ffffff => 0x200000000..0x23ffffff (64 MB)
         * Attributes: UXSX-UWSW-URSR (all)
         */

	addis	r4, 0, 0x1005		/* TLBSEL = TLB1(CAM), ESEL = 5 */ 
	ori	r4, r4, 0x0000
	mtspr	MAS0, r4
	addis	r5, 0, 0x8000		/* V = 1, IPROT = 0, TID = 0 */
	ori	r5, r5, 0x0800		/* TS = 0, TSIZE = 64 MB */
	mtspr	MAS1, r5
	addis	r6, 0, LOCAL_SDRAM1_ADRS >> 16	/* EPN = 0x20000000 */
	ori	r6, r6, 0x0000		/* WIMGE = 00000 */
	mtspr	MAS2, r6
	addis	r7, 0, LOCAL_SDRAM1_ADRS >> 16	/* RPN = 0x20000000 */
	ori	r7, r7, 0x003f		/* UXSX-UWSW-URSR = 11-11-11 */
	mtspr	MAS3, r7
	tlbwe
	tlbsync

        /*
         * Change WIMGE
         * TLB1 #6:  SDRAM - Global, TS=0, cached
         * 0x24000000..0x27ffffff => 0x240000000..0x27ffffff (64 MB)
         * Attributes: UXSX-UWSW-URSR (all)
         */

	addis	r4, 0, 0x1006		/* TLBSEL = TLB1(CAM), ESEL = 6 */ 
	ori	r4, r4, 0x0000
	mtspr	MAS0, r4
	addis	r5, 0, 0x8000		/* V = 1, IPROT = 0, TID = 0 */
	ori	r5, r5, 0x0800		/* TS = 0, TSIZE = 64 MB */
	mtspr	MAS1, r5
	addis	r6, 0, LOCAL_SDRAM2_ADRS >> 16	/* EPN = 0x24000000 */
	ori	r6, r6, 0x0000		/* WIMGE = 00000 */
	mtspr	MAS2, r6
	addis	r7, 0, LOCAL_SDRAM2_ADRS >> 16	/* RPN = 0x24000000 */
	ori	r7, r7, 0x003f		/* UXSX-UWSW-URSR = 11-11-11 */
	mtspr	MAS3, r7
	tlbwe
#endif  /* INCLUDE_LOCAL_SDRAM */

#if FALSE	/* this doesn't work yet */
	/*
	 * flash invalidate L1 I and D TLB entries, L2 TLB0 entries,
	 * and unprotected L2TLB1 entries to prevent overlap.
	 */

	li	r4, 0x2			/* r4 = L2TLB1_FI */
tstTlbClear0:
	mfspr	r5, MMUCSR0		/* r5 = MMUCSR0 */
	and.	r5, r5, r4
	bne	tstTlbClear0		/* loop to wait for clear */
	mtspr	MMUCSR0, r4		/* flash invalidate L2TLB1 */
tstTlbClear1:
	mfspr	r5, MMUCSR0		/* r5 = MMUCSR0 */
	and.	r5, r5, r4
	bne	tstTlbClear1		/* loop to wait for clear */
	li	r4, 0x1c		/* IL1MMU_FI | DL1MMU_FI | L2TLB0_FI */
	mtspr	MMUCSR0, r4		/* flash invalidate L1 and L2 */
        tlbsync
#endif  /* FALSE */


skipCold:

#ifdef INCLUDE_PCI
        /* Set the pciAutoconfig check to FALSE */
	xor     r5, r5, r5                /* Zero r5 */
	lis     r6, HIADJ(PCI_AUTO_CONFIG_ADRS)                   
	addi	r6, r6, LO(PCI_AUTO_CONFIG_ADRS)
	stw     r5, 0(r6)
#endif /* INCLUDE_PCI */

         /* Clear the CPU reservation bit */
#if FALSE  /* does not work, errata? */
        li      r0, 0
        lwarx   r3, r0, r0
        stwcx.  r3, r0, r0
#endif  /* does not work, errata? */
	
	xor	r6, r6 ,r6
	xor	r7, r7 ,r7
	mullw	r7, r7 ,r6
	lis	sp, HI(STACK_ADRS)
	ori	sp, sp, LO(STACK_ADRS)
	addi	sp, sp, -FRAMEBASESZ
	lis	r6, HI(romInit)
	ori	r6, r6, LO(romInit)
	lis	r7, HI(romStart)
	ori	r7, r7, LO(romStart)
	lis	r8, HI(ROM_TEXT_ADRS)
	ori	r8, r8, LO(ROM_TEXT_ADRS)
	sub	r6, r7, r6		/* routine - entry point */
	add	r6, r6, r8 		/* + ROM base */
	mtspr	LR, r6

	mr	r3, r2			/* restore startType */
	blr 
FUNC_END(_romInit)
FUNC_END(romInit)


/***************************************************************************
*
* resetEntry - rom entry point
*
* resetEntry is the first function to be called by the Book E core after
* reset. It is located at ROM address 0xfffff000. It is responsible for
* initializing key registers to a quiescent state, initializing the the
* TLB with a static memory mapping adequate for running the bootrom, and
* clearing the rest of the TLB. It sets up device access registers so
* the rest of the SRAM (or Boot Flash) can be correctly accessed.
* Finally, it sets up SRR0 and SRR1 with a safe MSR value and the
* instruction address of the romInit cold start entry point, and
* 'returns from interrupt' to synchronize processor context and continue
* the boot process in romInit.
*
* NOMANUAL
*
*/

#if   defined(_GNU_TOOL)
	.section .boot, "ax", @progbits
#elif defined(_DIAB_TOOL)
        .section .boot, 4, "rx"
#else
#error "Please add a correctly spelled .section directive for your toolchain."
#endif

FUNC_BEGIN(resetEntry)
FUNC_LABEL(_resetEntry)

        /* clear some registers */

	xor	r0, r0, r0
	mtspr	SRR0, r0
	mtspr	SRR1, r0
	mtspr	CSRR0, r0
	mtspr	CSRR1, r0
	mtspr	MCSRR0, r0
	mtspr	MCSRR1, r0
	mtspr	PID0, r0
	mtspr	PID1, r0
#ifdef	INIT_SKIP_PID2  /* sometimes causes TLB miss */
	nop
#else
	mtspr	PID2, r0
#endif	/* INIT_SKIP_PID2 */

	/*
	 * XXX - need to add RAM first (vector space?) or can get TLB misses
	 */

        /*
         * TLB1 #0:  Should have mapped the last 4kB by reset logic.
         *
         * TLB1 #1:  RAM - Protected, global, TS=0, cached
         * 0x00000000..0x0fffffff => 0x000000000..0x0fffffff (256 MB)
         * Attributes: UXSX-UWSW-URSR (all)
         */

	addis	r4, 0, 0x1001		/* TLBSEL = TLB1(CAM), ESEL = 1 */ 
	ori	r4, r4, 0x0000
	mtspr	MAS0, r4
	addis	r5, 0, 0xC000		/* V = 1, IPROT = 1, TID = 0 */
	ori	r5, r5, 0x0900		/* TS = 0, TSIZE = 256 MB */
	mtspr	MAS1, r5
	addis	r6, 0, DDR_SDRAM_ADRS1 >> 16	/* EPN = 0x00000000 */
	ori	r6, r6, 0x0006		/* WIMGE = 00110 */
	mtspr	MAS2, r6
	addis	r7, 0, DDR_SDRAM_ADRS1 >> 16	/* RPN = 0x00000000 */
	ori	r7, r7, 0x003f		/* UXSX-UWSW-URSR = 11-11-11 */
	mtspr	MAS3, r7
	tlbwe
	tlbsync

        /*
         * TLB1 #2:  RAM - Protected, global, TS=0, cached
         * 0x10000000..0x1fffffff => 0x100000000..0x1fffffff (256 MB)
         * Attributes: UXSX-UWSW-URSR (all)
         */

	addis	r4, 0, 0x1002		/* TLBSEL = TLB1(CAM), ESEL = 2 */ 
	ori	r4, r4, 0x0000
	mtspr	MAS0, r4
	addis	r5, 0, 0xC000		/* V = 1, IPROT = 1, TID = 0 */
	ori	r5, r5, 0x0900		/* TS = 0, TSIZE = 256 MB */
	mtspr	MAS1, r5
	addis	r6, 0, DDR_SDRAM_ADRS2 >> 16	/* EPN = 0x10000000 */
	ori	r6, r6, 0x0006		/* WIMGE = 00110 */
	mtspr	MAS2, r6
	addis	r7, 0, DDR_SDRAM_ADRS2 >> 16	/* RPN = 0x10000000 */
	ori	r7, r7, 0x003f		/* UXSX-UWSW-URSR = 11-11-11 */
	mtspr	MAS3, r7
	tlbwe
	tlbsync

	/*
	 * setup a TLB entry to move CCSRBAR from default reset location
	 * of 0xff700000 to 0xfe000000.  This will allow a maximum boot
	 * flash size of 16 MB instead of 8 MB to reside at the end of
	 * the memory space.
	 *
	 * In order to have a protected TLB entry to map 16 MB of flash
	 * and not to overlap the reset CCSRBAR location, this TLB entry
	 * will be overwritten after CCSRBAR is moved.
	 */

        /*
         * TLB1 #4:  CCSBAR_RST - Global, TS=0, non-cached
         * 0xff700000..0xff7fffff => 0xff7000000..0xff7fffff (1 MB)
         * Attributes: SW-URSR (no exec, user not writable)
         */

	addis	r4, 0, 0x1004		/* TLBSEL = TLB1(CAM), ESEL = 4 */ 
	ori	r4, r4, 0x0000
	mtspr	MAS0, r4
	addis	r5, 0, 0x8000		/* V = 1, IPROT = 0, TID = 0 */
	ori	r5, r5, 0x0500		/* TS = 0, TSIZE = 1 MB */
	mtspr	MAS1, r5
	addis	r6, 0, CCSBAR_RST >> 16	/* EPN = 0xff700000 */
	ori	r6, r6, 0x001e		/* WIMGE = 11110 */
	mtspr	MAS2, r6
	addis	r7, 0, CCSBAR_RST >> 16	/* RPN = 0xff700000 */
	ori	r7, r7, 0x0007		/* UXSX-UWSW-URSR = 00-01-11 */
	mtspr	MAS3, r7
	tlbwe
	tlbsync

        /*
         * TLB1 #3:  CCSRBAR - Protected, global, TS=0, non-cached
         * 0xfe000000..0xfe0fffff => 0xfe0000000..0xfe0fffff (1 MB)
         * Attributes: SW-URSR (no exec, user not writable)
         */

	addis	r4, 0, 0x1003		/* TLBSEL = TLB1(CAM), ESEL = 3 */ 
	ori	r4, r4, 0x0000
	mtspr	MAS0, r4
	addis	r5, 0, 0xC000		/* V = 1, IPROT = 1, TID = 0 */
	ori	r5, r5, 0x0500		/* TS = 0, TSIZE = 1 MB */
	mtspr	MAS1, r5
	addis	r6, 0, CCSBAR >> 16	/* EPN = 0xff700000 */
	ori	r6, r6, 0x001e		/* WIMGE = 11110 */
	mtspr	MAS2, r6
	addis	r7, 0, CCSBAR >> 16	/* RPN = 0xff700000 */
	ori	r7, r7, 0x0007		/* UXSX-UWSW-URSR = 00-01-11 */
	mtspr	MAS3, r7
	tlbwe
	tlbsync

	/* move CCSRBAR base address from reset of 0xff700000 */

	lis	r7, HIADJ(CCSBAR_RST)
	addi	r7, r7,LO(CCSBAR_RST)		/* r7 = 0xff700000 */
	lwz	r6, 0(r7)			/* r6 = current CCSBAR val */
	isync					/* context sync */
	lis	r6, HIADJ(CCSBAR >> 12)
	addi	r6, r6, LO(CCSBAR >> 12)
	stw	r6, 0(r7)			/* CCSRBAR = CCSBAR>>12 */
	lis	r7, HIADJ(resetEntry)
	addi	r7, r7,LO(resetEntry)		/* r7 = 0xfffff800 */
	lwz	r6, 0(r7)			/* r6 = don't cares */
	isync					/* context sync */
	lis	r7, HIADJ(CCSBAR)
	addi	r7, r7,LO(CCSBAR)		/* r7 = CCSBAR */
	lwz	r6, 0(r7)			/* r6 = new CCSBAR val */
	isync					/* context sync */

	/* overwrite TLB entry of CCSBAR_RST to prevent overlap with ROM */

        /*
         * TLB1 #4:  UTIL_ADRS - Protected, global, TS=0, non-cached
         * 0x28000000..0x28ffffff => 0x280000000..0x28ffffff (16 MB)
         * Attributes: UWSW-URSR (no exec)
         */

	addis	r4, 0, 0x1004		/* TLBSEL = TLB1(CAM), ESEL = 4 */ 
	ori	r4, r4, 0x0000
	mtspr	MAS0, r4
	addis	r5, 0, 0xC000		/* V = 1, IPROT = 1, TID = 0 */
	ori	r5, r5, 0x0700		/* TS = 0, TSIZE = 16 MB */
	mtspr	MAS1, r5
	addis	r6, 0, UTIL_ADRS >> 16	/* EPN = 0x28000000 */
	ori	r6, r6, 0x001e		/* WIMGE = 11110 */
	mtspr	MAS2, r6
	addis	r7, 0, UTIL_ADRS >> 16	/* RPN = 0x28000000 */
	ori	r7, r7, 0x000f		/* UXSX-UWSW-URSR = 00-11-11 */
	mtspr	MAS3, r7
	tlbwe
	tlbsync

        /*
         * TLB1 #0:  ROM - Protected, global, TS=0, non-cached
         * 0xff000000..0xffffffff => 0xff0000000..0xffffffff (16 MB)
         * Attributes: UXSX-URSR (not writable)
         */

	addis	r4, 0, 0x1000		/* TLBSEL = TLB1(CAM), ESEL = 0 */ 
	ori	r4, r4, 0x0000
	mtspr	MAS0, r4
	addis	r5, 0, 0xC000		/* V = 1, IPROT = 1, TID = 0 */
	ori	r5, r5, 0x0700		/* TS = 0, TSIZE = 16 MB */
	mtspr	MAS1, r5
	addis	r6, 0, BOOT_FLASH_MAP_ADRS >> 16 /* EPN = 0xff000000 */
	ori	r6, r6, 0x0016		/* WIMGE = 11110 */
	mtspr	MAS2, r6
	addis	r7, 0, BOOT_FLASH_MAP_ADRS >> 16 /* RPN = 0xff000000 */
	ori	r7, r7, 0x0033		/* UXSX-UWSW-URSR = 11-00-11 */
	mtspr	MAS3, r7
	tlbwe
	tlbsync

#undef USE_RFI	/* not supported */
#ifdef USE_RFI
	mtspr	SRR0, r4
	mfmsr	r0
	mtspr	SRR1, r0
	rfi
	/* mtspr	LR, r4 */
#else	/* USE_RFI */
	b	cold
#endif	/* USE_RFI */

FUNC_END(resetEntry)


/***************************************************************************
*
* resetVector - hardware reset vector
*
* At power-on, the processor starts executing at ROM address 0xfffffffc --
* the top of the address space -- which must be a jump to resetEntry.
* This is defined as a separate "section" to assist the linker in locating
* it properly.
*
* NOMANUAL
*
*/

#if   defined(_GNU_TOOL)
	.section .reset, "ax", @progbits
#elif defined(_DIAB_TOOL)
	.section .reset, 4, "rx"
#else
#error "Please add a correctly spelled .section directive for your toolchain."
#endif

FUNC_BEGIN(resetVector)
	b	resetEntry
FUNC_END(resetVector)