config.h

MPC8560 for vxwork BSP

#ifdef	INCLUDE_CPM
#   if defined(INCLUDE_PRIMARY_FCC_END) || defined(INCLUDE_SECONDARY_FCC_END)
#       define INCLUDE_END
#       define INCLUDE_MOT_FCC_END
#       define INCLUDE_MOTFCCEND
#       /* may need to define INCLUDE_MEZZ_COM2 */
#   endif
#else	/* INCLUDE_CPM */
#   undef  INCLUDE_PRIMARY_FCC_END
#   undef  INCLUDE_SECONDARY_FCC_END
#endif	/* INCLUDE_CPM */


/* MAC Address configuration */

#define WR_MAC0                 0x00	/* WR portion of MAC (MSB->LSB) */
#define WR_MAC1                 0xa0
#define WR_MAC2                 0x1e

#define USR_MAC3a               0xb4	/* user portion of MAC address */
#define USR_MAC3b               0xb5	/* user portion of MAC address */
#define USR_MAC3c               0xb6	/* user portion of MAC address */
#define USR_MAC3d               0xb7	/* user portion of MAC address */
#define USR_MAC4                0x2e
#define USR_MAC5                0x3f

#define ENET_DEFAULT		0x1ea00000


/* Remove unsupported drivers */

#undef INCLUDE_SM_NET
#undef INCLUDE_SM_SEQ_ADD


/* TFFS configuration
 *
 * Define INCLUDE_TFFS here if TrueFFS is needed.  Optionally, TFFS
 * can be used to program the bootrom when INCLUDE_TFFS_BOOTROM_OVERWRITE 
 * is defined.  Use caution to avoid erasing the bootrom accidentally.
 */

#define	INCLUDE_TFFS
#undef  INCLUDE_TFFS_BOOTROM_OVERWRITE	/* define only when flashing bootrom */
#undef  INCLUDE_DISK_UTIL

/* PCI configuration
 *
 * PCI is not currently supported by this BSP
 */

#define INCLUDE_PCI_AUTOCONF

/*
 *  CPU Addr                                         PCI Addr
 *  PCI_LOCAL_MEM_BUS     -------------------------- PCI_MSTR_MEM_BUS
 *                        -                        - 
 *                        -                        -
 *  PCI_LOCAL_MEM_BUS +   -------------------------- PCI_MSTR_MEM_BUS +
 *  PCI_LOCAL_MEM_SIZE    -                        - PCI_MSTR_MEM_SIZE
 *                        -                        - 
 *                        -                        ----- PCI Bridge   
 *                        -                        -     configuration regs
 *                        -                        - 
 *  CPU_PCI_MEM_ADRS      -------------------------- PCI_MEM_ADRS
 *                        -                        - 
 *                        -                        - 
 *  CPU_PCI_MEMIO_ADRS    -------------------------- PCI_MEMIO_ADRS
 *                        -                        - 
 *                        -                        - 
 *  CPU_PCI_IO_ADRS       -------------------------- PCI_IO_ADRS
 *                        -                        -
 *                        -                        -
 *  CPU_PCI_IO_ADRS +     -------------------------- PCI_IO_ADRS +
 *  CPU_PCI_IO_SIZE       -                        - PCI_IO_SIZE
 *                        -                        -
 *                        -                        -
 *                        ----PCI Bridge           -
 *                        -------------------------- 4GBytes 
 */

/* For custom sysPciAutoConfig.c */

/* PCI based addresses */

#define PCI_MEM_ADRS		0x90000000 
#define PCI_MEM_SIZE		0x01000000	/* 16MB */
#define PCI_MEMIO_ADRS		0xa0000000
#define PCI_MEMIO_SIZE		0x01000000	/* 16MB */
#define PCI_IO_ADRS		0xb0000000 
#define PCI_IO_SIZE		0x01000000	/* 16MB */

#define PCI_MEM_SIZE_MASK	PCI_ATTR_WS_16M
#define PCI_MEMIO_SIZE_MASK	PCI_ATTR_WS_16M
#define PCI_IO_SIZE_MASK	PCI_ATTR_WS_16M

/* CPU based addresses */

#define CPU_PCI_MEM_ADRS	0x90000000
#define CPU_PCI_MEM_SIZE	PCI_MEM_SIZE 
#define CPU_PCI_MEMIO_ADRS	0xa0000000
#define CPU_PCI_MEMIO_SIZE	PCI_MEMIO_SIZE 
#define CPU_PCI_IO_ADRS		0xb0000000
#define CPU_PCI_IO_SIZE		PCI_IO_SIZE

/* CPU from PCI bus */

#define PCI_MSTR_MEM_BUS	0x40000000	/* align on 512 MB */
#define PCI_MSTR_MEM_SIZE	LOCAL_MEM_SIZE
#define PCI_BRIDGE_PIMMR_BASE_ADRS	0x30000000

/* CPU Address that is visible from PCI */

#define PCI_LOCAL_MEM_BUS	0x00000000
#define PCI_LOCAL_MEM_SIZE	PCI_MSTR_MEM_SIZE
#define PCI_LOCAL_MEM_SIZE_MASK	PCI_ATTR_WS_512M

#ifndef	PCI_CFG_TYPE
#   ifdef INCLUDE_PCI_AUTOCONF
#       define PCI_CFG_TYPE PCI_CFG_AUTO
#   else
#       define PCI_CFG_TYPE PCI_CFG_FORCE
#   endif /* INCLUDE_PCI_AUTOCONF */
#endif	/* PCI_CFG_TYPE */

/* Saving boot parameters */

/* NVRAM configuration */

#define INCLUDE_NV_RAM
#ifdef  INCLUDE_NV_RAM
#   define NV_RAM_ADRS		0x28b00000
#   undef  NV_RAM_SIZE
#   define NV_RAM_SIZE		0x2000 /* 8KB */
#   define NV_RAM_INTRVL	1
#   undef  NV_BOOT_OFFSET
#   define NV_BOOT_OFFSET	0
#   define NV_MAC_ADRS_OFFSET   0x200

#   define NV_RAM_WR_ENBL	sysNvRamWrEnbl()
#   define NV_RAM_WR_DSBL	sysNvRamWrDsbl()
#   define NV_RAM_READ		sysNvRamRead
#   define NV_RAM_WRITE		sysNvRamWrite
#endif  /* INCLUDE_NV_RAM */
 
/* Using flash to store boot params is not supported */

#undef INCLUDE_FLASH
#ifdef INCLUDE_FLASH
#   define SYS_FLASH_TYPE	FLASH_28F640J3A    /* flash device type */
#   define FLASH_WIDTH		2
#   define FLASH_CHIP_WIDTH	2
#   define FLASH_WIDTH_SPECIAL_2
#   define FLASH_SEGMENT_SIZE	0x20000

#   define FLASH_ADRS		(0xff800000 + 0x700000 - FLASH_SEGMENT_SIZE)
#   define FLASH_SIZE		FLASH_SEGMENT_SIZE
#   define FLASH_SIZE_WRITEABLE	FLASH_SEGMENT_SIZE
#   undef  NV_RAM_SIZE
#   define NV_RAM_SIZE		FLASH_SEGMENT_SIZE
#   undef  FLASH_NO_OVERLAY
#   undef  NV_BOOT_OFFSET
#   define NV_BOOT_OFFSET	FLASH_SEGMENT_SIZE - 0x200
#endif  /* INCLUDE_FLASH */

#ifndef NV_RAM_SIZE
#   define NV_RAM_SIZE		NONE
#endif


/* Memory addresses */
 
#define LOCAL_MEM_SIZE		0x20000000	/* 512 MB memory available */
#define LOCAL_MEM_LOCAL_ADRS	0x00000000	/* Base of RAM */

 
/* Toolchain related defines */

#undef	INCLUDE_PPC_FPU		/* e500 has no std PowerPC fp unit */
#undef	INCLUDE_HW_FP		/* disable hardware fp support */
#define	INCLUDE_SW_FP		/* enable software fp support */


/* Power Management */
#define	DEFAULT_POWER_MGT_MODE	VX_POWER_MODE_DISABLE

#ifdef INCLUDE_MMU_BASIC

#define INCLUDE_AIM_MMU_CONFIG
#define INCLUDE_MMU_OPTIMIZE 

#define INCLUDE_AIM_MMU_SHOW

#define INCLUDE_AIM_MMU_MEM_POOL_CONFIG

/* 
 * The following parameters are to configure initial memory usage for 
 * page table and region tables and in event of running out the increment 
 * of memory allocation and is specified as a number of MMU pages (4KByte
 * blocks). 
 */
#define AIM_MMU_INIT_PT_NUM 0x40
#define AIM_MMU_INIT_PT_INCR 0x20
#define AIM_MMU_INIT_RT_NUM 0x10
#define AIM_MMU_INIT_RT_INCR 0x10

/* This write protects the page tables */
#define INCLUDE_AIM_MMU_PT_PROTECTION

/* 
 * INCLUDE_LOCK_TEXT_SECTION Requires use of CAM entries which can 
 * possibly be already used in sysStaticTlbDesc. Also the larger the 
 * page size that can be used the less CAM entries required so aligning 
 * RAM_LOW_ADRS on a large page size boundary is usually necessary.
 * Locking the text section should increase performance because no 
 * Instruction TLB misses are taken within the text section.
 */

#define INCLUDE_LOCK_TEXT_SECTION     
#undef INCLUDE_PAGE_SIZE_OPTIMIZATION /* Not available for 85XX */

#endif /* INCLUDE_MMU_BASIC */

/*
 * The constants ROM_XXX_ADRS, ROM_SIZE, and RAM_XXX_ADRS are defined
 * in both config.h and Makefile.  All definitions for these constants
 * must be identical.
 */
 
#ifndef RAM_LOW_ADRS
#define	RAM_LOW_ADRS		0x00100000
#endif  /* RAM_LOW_ADRS */

#ifndef RAM_HIGH_ADRS
#define	RAM_HIGH_ADRS		0x00e00000
#endif  /* RAM_HIGH_ADRS */

#define	ROM_BASE_ADRS		0xFFF00000
#define	ROM_TEXT_ADRS		0xFFF00100
#define	ROM_SIZE		0x00100000

#define	USER_RESERVED_MEM	0x00000000

#ifdef __cplusplus
    }
#endif /* __cplusplus */

#endif  /* INCconfigh */

#if defined(PRJ_BUILD)
#    include "prjParams.h"
#endif /* PRJ_BUILD */