config.h

MPC8560 for vxwork BSP

/* config.h - wrSbc85xx configuration header file */

/* Copyright 2002-2006 Wind River Systems, Inc. */

/*
modification history
--------------------
01y,28Jul06,tor  incorporate PCI support, VXBUS mods
01x,06feb06,wap  Add INCLUDE_PARAM_SYS
01w,15sep05,to   revision update for VxWorks 6.2.
01v,06apr05,dtr  Add in SNOOP for cache.
01v,13jun05,pcm  removed INCLUDE_DOSFS
01u,27aug04,mil  Modified TFFS macros.
01t,27sep04,mil  Added conditional for L1 parity error handler (SPR 102069).
01s,30sep04,dtr  Add in AIM MMU configuration.
01r,30jul04,md   use default PM_RESERVED_MEM 
01r,14sep04,j_b  remove INCLUDE_SHOW_ROUTINES (SPR 101418)
01q,10sep04,mil  Make RAM_LOW_ADRS and RAM_HIGH_ADRS conditional.
01p,10jun04,mil  Added L1 errata workaround.
01o,08jun04,mdo  Change MMU configuration - dependency is elsewhere.
01n,26may04,mil  Fixed L2 not being enabled by default.
01m,10may04,mil  Repositioned defines of cache macros.
01l,05may04,mil  Removed TSEC cache undef, added cache settings, N boot cmd.
01k,02feb04,mil  Added config for L2 cache and L2 SRAM.
01j,23oct03,mil  Cleanup.
01i,20oct03,mil  Changed TFFS to optional, removed CTORS_DTORS.
01h,17oct03,mil  Fixed RAM_HIGH_ADRS value.
01g,12sep03,mil  Updated settings for cache, clock and interrupt.
01f,29jul03,dtr  Added snoop and disable L2 because of dcbi/dcbst issue.
01e,22jul03,mil  Added flash parameters.
01d,07jul03,mil  Added CPM and SCC.
01c,25jun03,mil  Added prjParams.h for project build.
01b,09oct02,dtr  Added more defines for more complete base for BSP.
01a,03oct02,dtr  Created.
*/


#ifndef	INCconfigh
#define	INCconfigh

#ifdef __cplusplus
    extern "C" {
#endif /* __cplusplus */


#define BSP_VER_1_1     1
#define BSP_VER_1_2     1
#define BSP_VERSION     "2.0"
#define BSP_REV         "/5"

#define INCLUDE_ECC

#include "configAll.h"
#include "wrSbc85xx.h"

#define INCLUDE_VXBUS
#define INCLUDE_SHOW_ROUTINES
#define INCLUDE_VXBUS_SHOW
#define INCLUDE_PARAM_SYS
#define INCLUDE_HWMEM_ALLOC
#define HWMEM_POOL_SIZE 50000
#define INCLUDE_PLB_BUS

#define INCLUDE_MOT_TSEC_HEND
#define INCLUDE_MII_BUS
#define INCLUDE_BCM54XXPHY
#define INCLUDE_GENERICPHY
#define INCLUDE_END

#define	INCLUDE_PCI 
#define INCLUDE_PCI_BUS
#define DRV_PCIBUS_M85X0
#define DRV_RESOURCE_M85XXCCSR
#define DRV_SIO_NS16550
#define INCLUDE_SIO_UTILS

#define INCLUDE_DMA_SYS

#ifdef INCLUDE_PCI_BUS
#undef INCLUDE_GEI_HEND
#endif /* INCLUDE_PCI_BUS */

#define INCLUDE_IFCONFIG

/* Boot device and file location */

#define DEFAULT_BOOT_LINE \
"mottsec(0,0)host:/target/config/wrSbc85xx/vxWorks h=90.0.0.3 e=90.0.0.50 u=vxworks"
#define ALT_BOOT_LINE \
"motfcc(0,0)host:/target/config/wrSbc85xx/vxWorks h=90.0.0.3 e=90.0.0.50 u=vxworks"
#undef	USE_ALT_BOOTLINE	/* define when no bootrom or override NVRAM */


/* Clock speed and source  */

#define	FREQ_33_MHZ	 33333333
#define	FREQ_66_MHZ	 66666666
#define	FREQ_100_MHZ	 99999999
#define	FREQ_133_MHZ	133333333
#define	FREQ_266_MHZ	266666666
#define	FREQ_USR_MHZ	196800000	/* expr result CCB @ 200 MHz */

#define	OSCILLATOR_FREQ		FREQ_66_MHZ	/* oscillator installed */
/* make sure PLAT_FREQ_DEFAULT matches CCB CLK rate per DIP switches */
#define PLAT_FREQ_DEFAULT	(OSCILLATOR_FREQ * 3)  /* 3:1 CCB ratio */


/* MMU and cache */

/* To allow recovery from a parity error in the L1 instruction or data
 * cache, the following macro can be defined.  The cache will be put 
 * in writethrough mode and hence has a slight penalty on performance.
 * This is available in VxWorks 6.0 only.  
 *
 * If this macro is not defined (including VxWorks 6.0 and 5.5.x),
 * it will default to allow recovery from a parity error in the L1
 * instruction cache, but not the data cache.  Writethrough is not
 * required and thus no performance impact.
 */

#undef E500_L1_PARITY_RECOVERY

#ifdef E500_L1_PARITY_RECOVERY
  /* *** NOTE FOR PROJECT FACILITY USERS ***
   * Needs to use WRITETHROUGH, building with Project Facility must also
   * change USER_D_CACHE_MODE and USER_I_CACHE_MODE in Project Facility.
   */

# define CACHE_LIBRARY_MODE     (CACHE_COPYBACK | CACHE_SNOOP_ENABLE)
# define CAM_DRAM_CACHE_MODE    _MMU_TLB_ATTR_M
# define TLB_CACHE_MODE         (VM_STATE_CACHEABLE | \
                                VM_STATE_MEM_COHERENCY)

#else  /* E500_L1_PARITY_RECOVERY */

# define CACHE_LIBRARY_MODE     CACHE_COPYBACK 
# define CAM_DRAM_CACHE_MODE    0
# define TLB_CACHE_MODE         VM_STATE_CACHEABLE

  /* If E500_L1_PARITY_RECOVERY is not defined, use local BSP handler.
   * Works for L1 instr cache but not data cache.  Writethrough not needed.
   */  
# if defined(INCLUDE_CACHE_SUPPORT) && defined(USER_I_CACHE_ENABLE)
#   if (defined(_WRS_VXWORKS_MAJOR) && (_WRS_VXWORKS_MAJOR >= 6))
#     define INCLUDE_L1_IPARITY_HDLR              /* VxWorks 6.x */
#   else  /* _WRS_VXWORKS_MAJOR */
#     define INCLUDE_L1_IPARITY_HDLR_INBSP        /* VxWorks 5.5.x */
#   endif /* _WRS_VXWORKS_MAJOR */
# endif  /* INCLUDE_CACHE_SUPPORT && USER_I_CACHE_ENABLE */

#endif  /* E500_L1_PARITY_RECOVERY */


#define	INCLUDE_MMU_BASIC
#define	USER_I_MMU_ENABLE
#define	USER_D_MMU_ENABLE

#ifdef CACHE_LIBRARY_MODE
# define ICACHE_MODE	CACHE_LIBRARY_MODE
# define DCACHE_MODE	CACHE_LIBRARY_MODE
#else  /* CACHE_LIBRARY_MODE */
# define ICACHE_MODE	CACHE_COPYBACK
# define DCACHE_MODE	CACHE_COPYBACK
#endif  /* CACHE_LIBRARY_MODE */

#define	INCLUDE_CACHE_SUPPORT
#define	USER_D_CACHE_ENABLE
#undef	USER_D_CACHE_MODE
#define	USER_D_CACHE_MODE	(DCACHE_MODE)
#define	USER_I_CACHE_ENABLE
#undef	USER_I_CACHE_MODE
#define	USER_I_CACHE_MODE	(ICACHE_MODE)

#define	INCLUDE_L2_CACHE
#define	INCLUDE_L2_SRAM

#if defined(INCLUDE_L2_CACHE) && !defined(INCLUDE_CACHE_SUPPORT)
# warning "Excluding L2 cache because INCLUDE_CACHE_SUPPORT is not defined"
# undef INCLUDE_L2_CACHE        /* L2 requires L1 */
#endif

#define	L2SRAM_ADDR		0x7FFC0000
#define	L2SRAM_WINDOW_SIZE	0x40000 

#if (defined(INCLUDE_L2_CACHE) && defined(INCLUDE_L2_SRAM))
# define L2_CACHE_SIZE		L2SIZ_128KB
# define L2_SRAM_SIZE		L2SIZ_128KB
#elif (defined(INCLUDE_L2_CACHE) && !defined(INCLUDE_L2_SRAM))
# define L2_CACHE_SIZE		L2SIZ_256KB
# define L2_SRAM_SIZE		0
#else
# define L2_SRAM_SIZE		L2SIZ_256KB
# define L2_CACHE_SIZE		0
#endif

#define INCLUDE_BRANCH_PREDICTION


/* Serial channel and TTY
 *
 * INCLUDE_CPM should be defined for a MPC8560-based board, or undefined
 * otherwise.  It should be found in EXTRA_DEFINE in the Makefile for a
 * wrSbc8560 board, where the on-board DUART device will be used.  On a
 * wrSbc8540 board, the serial is the on-chip DUART device.  Both the
 * on-board or on-chip devices share the same physical com port.
 *
 * If a mezzanine card with a second serial port is installed on the
 * wrSbc8560, define INCLUDE_MEZZ_COM2 to avoid no output from both
 * COM1 and COM2.
 */

#undef INCLUDE_MEZZ_COM2

#ifdef INCLUDE_SCC_SERIAL
#  define NUM_TTY_BSP 2	       
#else 
#  define NUM_TTY_BSP 0
#endif  /* INCLUDE_SCC_SERIAL */

#if ! (defined(INCLUDE_SCC_SERIAL) || defined(DRV_SIO_NS16550))
#  undef  INCLUDE_TTY_DEV
#warning no console
#endif

#ifdef DRV_SIO_NS16550
#define NUM_TTY_VXBUS	4
#else
#define NUM_TTY_VXBUS	0
#endif

#undef  NUM_TTY
#define NUM_TTY	(NUM_TTY_BSP + NUM_TTY_VXBUS)

/* EPIC configuration
 *
 * Define INCLUDE_EPIC_CRT_INTR to include EPIC critical handler
 */

#undef	INCLUDE_EPIC_CRT_INTR


/* Optional features support */

#define	INCLUDE_SPE			/* signal processing engine */
#define	INCLUDE_AUX_CLK			/* aux clock */
#undef	INCLUDE_TIMESTAMP		/* optional timestamp */
#undef	INCLUDE_SYS_HW_INIT_0		/* extended vectors */
#define	INCLUDE_USR_FLASH		/* maps usr (SIMM) flash */
#define	INCLUDE_LOCAL_SDRAM		/* maps LBC SDRAM */


/* Network driver config */

#undef	INCLUDE_PRIMARY_FCC_END		/* will undef below if !INCLUDE_CPM */
#undef	INCLUDE_SECONDARY_FCC_END	/* will undef below if !INCLUDE_CPM */